Signal description and bus operation – Motorola DSP96002 User Manual

Page 4

MOTOROLA

DSP96002 USER’S MANUAL

2 - 1

SECTION 2

SIGNAL DESCRIPTION AND BUS OPERATION

2.1

PINOUT

The functional signal groups of the DSP96002 are shown in Figure 2-2, and are described in the following

sections. A pin allocation summary is shown in Figure 2-1. Specific pinout and timing information is avail-

able in the DSP96002 Technical Data Sheet (DSP96002/D).

2.1.1 Package

The DSP96002 is available in a 223 pin PGA package. There are 176 signal pins (including 5 spares), 17
power pins and 30 ground pins. All packaging information is available in the data sheet.

2.1.2 Interrupt And Mode Control (4 Pins)

—

–

T (Reset) - active low, Schmitt trigger input.

—

–

T is internally synchronized

to the input clock (CLK). When asserted, the chip is placed in the reset state and the

internal phase generator is reset. The Schmitt trigger input allows a slowly rising input

(such as a capacitor charging) to reliably reset the chip. If

—

–

T is deas-

serted synchronous to the input clock (CLK), exact startup timing is guaranteed, allow-

ing multiple processors to startup synchronously and operate together in "lock-step".

When the

—

–

T pin is deasserted, the initial chip operating mode is latched

from the MODA, MODB and MODC pins.

MODA/

—

–

A(Mode Select A/External Interrupt Request A) - active low input, internally

synchronized to the input clock (CLK). MODA/

—

–

A selects the initial chip

operating mode during hardware reset and becomes a level sensitive or negative edge

triggered, maskable interrupt request input during normal instruction processing.

MODA, MODB and MODC select one of 8 initial chip operating modes, latched into the

operating mode register (OMR) when the

—

–

T pin is deasserted. If

—

–

A is asserted synchronous to the input clock (CLK), multiple processors can be

resynchronized using the WAIT instruction and asserting

—

–

A to exit the wait

state. If the processor is in the STOP standby state and

—

–

A is asserted, the

processor will exit the STOP state.