Motorola DSP96002 - Manual (Page 788)

6 MOTOROLA
2.3 CACHE OPERATION
During cache operation each instruction is fetched on demand, only when it is needed.
When the core generates an address for an instruction fetch, the cache controller com-
pares the tag field portion of the physical address to the tag values currently stored in the
tag register file. The tag values are the memory sector’s 25 upper bits currently mapped
into the cache.
When a tag match occurs (i.e. sector hit), then the valid-bit of the corresponding word in
that cache sector is checked. If the valid-bit is set, meaning the word in the cache has al-
ready been brought to the cache and is valid, then that word is fetched from the cache
location corresponding to the desired address. This event is called a cache hit, meaning
that both the sector and its corresponding instruction word are present and valid in the in-
struction cache. The sector replacement unit (SRU) updates the used sector state accord-
ing to the LRU algorithm.
When a tag match occurs, but the desired word is not valid in the cache (corresponding
valid-bit cleared, indicating a word miss), then the cache initiates a read cycle from the
external program memory. The fetched instruction is both sent to the core and copied to
the relevant sector location. Then the valid-bit of that word is set. All of this is done in par-
allel with normal execution and does not require any additional clock or memory cycles.
The SRU updates the used sector state according to the LRU algorithm.
If no match occurs between the tag field and all sector tag registers, meaning that the
memory sector containing the requested word is not present in the cache, the situation is
called a sector miss, which is another form of a cache miss. When a sector miss occurs,
the cache’s SRU selects the sector to be replaced. The cache controller then flushes the
selected cache sector by resetting all corresponding valid-bits, loads the corresponding
tag register with the new tag field, and at the same time initiates an external instruction
read cycle from the physical address requested by the core. When the data arrives from
external memory, it is transferred to the core, and at the same time the cache controller
copies it to the word location in the cache sector, specified by the 7 LSBs of the address,
and sets the corresponding valid-bit. The SRU now updates the new situation in the sector
replacement control unit.
In PRAM mode, when the cache is disabled, fetches are done internally or externally as
in the first revision of the DSP96002.
2.4 INSTRUCTION CACHE PROGRAMMING MODEL
2.4.1 Operating Mode Register (OMR)
To support the cache operation, the Operating Mode Register (OMR) now features a new