Motorola DSP96002 - Manual (Page 436)

A - 248 DSP96002 USER’S MANUAL MOTOROLA
IFcc Integer iF IFcc
Conditional Instruction
without CCR Update
Operation:
If cc, then opcode operation
S
→
D
Assembler Syntax:
Opcode-Operands S,D IFcc
IFcc
Description:
If the specified integer condition is true, transfer data from the specified source S to the specified destina-
tion D. Also, store result(s) of the specified Data ALU operation. If the specified condition is false, no
destinations are altered. The CCR, ER and IER registers are never updated with the condition codes gen-
erated by the Data ALU operation. If no register move is specified, this instruction is assembled with a R0
to R0 move.
"cc" may specify the following conditions:
Mnemonic Condition
CC (HS) - carry clear (higher or same) C = 0
CS (LO) - carry set (lower) C = 1
EQ - equal Z = 1
GE - greater or equal N && V = 0
GT - greater than Z v (N && V) = 0
HI - higher Z v C = 0
LE - less or equal Z v (N && V) = 1
LS - lower or same Z v C = 1
LT - less than N && V = 1
MI - minus N = 1
NE(Q) - not equal Z = 0
PL - plus N = 0
VC - overflow clear V = 0
VS - overflow set V = 1
AL - always true n.a.
CAUTION
See restrictions in Section A.10.6 concerning Rn, Mn, and Nn registers as a
destination.
Move Move