Motorola DSP96002 - Manual (Page 135)

MOTOROLA DSP96002 USER’S MANUAL 7 - 49
7.5.3.7 DCS DMA Transfer Mode – (DTM1–DTM0) Bits 25,26
DMA Transfer Mode bits (DTM1-DTM0) specify the mode of operation of the DMA channel. DTM1-DTM0
are cleared by Hardware and Software Reset.
When DTM1-DTM0=00, a single block is transferred, the length of the block is determined by the counter,
the transfer is initiated by setting the DE bit, and the transfer is completed when the counter decrements to
zero.
When DTM1-DTM0=01, a single block is transferred, the length of the block is determined by the counter,
the transfer is initiated by the first DMA request after DE is set to 1, and the transfer is completed when the
counter decrements to zero.
When DTM1-DTM0=10, a single block is transferred, the length of the block is determined by the counter,
each DMA request will transfer a single word while DE=1, and the transfer is completed when the counter
decrements to zero.
When DTM1-DTM0=11, a single word is transferred each time a DMA request is received while DE=1. The
counter is ignored in this mode.
7.5.3.8 DCS DMA Transfer Done Status (DTD) Bit 28
The read-only DMA Transfer Done Status bit is set when the last word during a Single Block transfer is
stored in the destination, stopping DMA operation. At the same time, DE will be cleared. The last transfer is
defined as the one where the DMA Counter reaches zero, or the transfer being done when the DE bit is
cleared by the core. If DIE is set (DMA Interrupt enabled), then DTD=1 will cause a DMA interrupt request.
When the DMA Interrupt is disabled (DIE=0), the core may verify the DMA status by polling this bit. DTD is
set by Hardware and Software Reset. DTD is cleared by setting DE.
7.5.3.9 DCS DMA Interrupt Enable Control Bit (DIE) Bit 30
When the DMA Interrupt Enable (DIE) bit is set, the DMA interrupt occurs when DTD is set. When DIE is
cleared, the DMA interrupt is disabled. Cleared by Hardware and Software Reset.
7.5.3.10 DCS DMA Channel Enable Control Bit (DE) Bit 31
The DE bit enables DMA Controller operation. Setting DE will clear DTD. Setting DE will trigger a single
block DMA transfer if DTM1-DTM0=00. Setting DE will enable transfers in DMA modes that use a request-
ing device as trigger. DE is cleared by Hardware and Software Reset, and by end of DMA transfer if a Single
DTM1 DTM0 Transfer Mode
0 0 Single Block, Trig. by DE Bit, DMA Request Ignored
0 1 Single Block, Trig. by First DMA Request
1 0 Single Block, Word Transfer Trig. by DMA Request
1 1 Single Word, Triggered by DMA Request
DIE DMA Interrupt
0 Disabled
1 Enabled