Motorola DSP96002 - Manual (Page 735)

C-12 DSP96002 USER’S MANUAL MOTOROLA
Figure C-10b. Automatic Format Conversion – Double Precision
63 62 52 51 0
S Fraction
21 20
e
63 62 52 51 0
S Fraction
21 22
e
95 94 75 74 64 63 62 32 31 11 10 0
S e 0 Fraction i
L Data Memory
L Data Memory
i = 1 when normalized
i = 0 when unnormalized
*
* – Bits 11-31 (in Dn) or 0-20
(in L memory) are zero when
the register contains an SEP
result.
Dn
mode, the number is "corrected" when used as an operand for floating point calculations, at the expense of
extra cycles introduced for normalization.
The 8-bit exponent of the SP source is translated into an 11-bit exponent by copying the 7 least significant
bits of the source exponent into the seven least significant bits of the destination. The most significant bit of
the 8-bit exponent of the source is copied to the most significant bit of the exponent of the destination. The
remaining 3 bits of the destination’s exponent are set if the number is a NaN or infinity, otherwise they are
the inverted MSB of the source’s exponent. Inverting the MSB effectively changes the bias from 127 to
1023.
When moving single precision numbers from the data ALU to memory (see Figure C-10a), the above pro-
cess is reversed. The 23 most significant bits of the fraction are moved to the 23 fraction bits of the desti-
nation. Note that the contents of the data ALU register may have more than 23 fractional bits if it was the
result of a previous DP move or SEP arithmetic operation; in this case, the fraction is simply truncated.
The MSB of the 11-bit exponent of the source in the data ALU is moved to the MSB of the exponent of the
destination. The 7 LSBs of the exponent of the source are copied to the seven LSBs of the exponent of the
source. Note that if the source was not a SP number (result of a DP move or a SEP arithmetic operation),
an incorrect exponent may be moved. Therefore, care must be taken to always round results to SP be-
fore moving them to memory as single precision numbers.
When moving DP numbers into the Data ALU from memory (see Figure C-10b), the 52 bit fraction of the