beautypg.com

Motorola DSP96002 User Manual

Page 71

background image

5 - 18

DSP96002 USER’S MANUAL

MOTOROLA

(pointers) rather than moving large blocks of data. The contents of the address modifier register Mn defines

the type of address arithmetic to be performed for addressing mode calculations, and for the case of mod-

ulo arithmetic, the contents of Mn also specifies the modulus. All address register indirect modes may be

used with any address modifier type. Each address register Rn has its own modifier register Mn associated

with it.

5.8.1 Linear Modifier

The address modification is performed using normal 32-bit (modulo 4,294,967,296) linear arithmetic (two’s

complement). A 32-bit offset Nn, or immediate data (+1, -1, or a displacement value) may be used in the

address calculations. The range of values may be considered as signed (Nn from -2,147,483,648 to

+2,147,483,647) or unsigned (Nn from 0 to +4,294,967,295). There is no arithmetic differences between

these two data representations. Addresses are normally considered unsigned, data is normally considered

signed.

5.8.2 Reverse Carry Modifier

The address modification is performed by propagating the carry in the reverse direction, i.e., from the MSB

to the LSB. This is equivalent to bit-reversing the contents of Rn and the offset value Nn, adding normally

and then bit-reversing the result. If the (Rn)+Nn addressing mode is used with this address modifier, and

Nn contains the value 2

K-1

(a power of two), then postincrementing by Nn is equivalent to bit-reversing the

K LSBs of Rn, incrementing Rn by 1, and bit-reversing the K LSBs of Rn. This address modification is use-

ful for 2

K

point FFT addressing. The range of values for Nn is 0 to +4,294,967,295. This allows bit-reversed

addressing for FFTs up to 8,589,934,592 points.

As an example, consider a 1024 point FFT with real data stored in X memory and imaginary data stored in

Y memory. Then Nn would contain the value 512 and postincrementing by +N would generate the address

sequence 0, 512, 256, 768, 128, 640, ... This is the scrambled FFT data order for sequential frequency

points from 0 to 2*pi. For proper operation the reverse carry modifier restricts the base address of the bit

reversed data buffer to an integer multiple of 2

K

, such as 1024, 2048, 3072, etc. The use of addressing

modes other than postincrement by Nn is possible but may not provide a useful result.

5.8.3 Modulo Modifier

The address modification is performed modulo M, where M is permitted to range from 2 to +16,777,216.

Modulo M arithmetic causes the address register value to remain within an address range of size M defined

by a lower and upper address boundary. The value M-1 is stored in the modifier register Mn, thus allowing

a modulo size range from 2 to 16,777,216. The lower boundary (base address) value must have zeroes in

the k LSBs, where 2

k

>= M , and therefore must be a multiple of 2

k

. The upper boundary is the lower bound-

ary plus the modulo size minus one (base address plus M-1).

For example, to create a circular buffer of 24 stages, M is chosen as 24 and the lower address boundary

must have its 5 LSBs equal to zero (2

k

>= 24, thus k >= 5). The Mn register is loaded with the value 23

(m-1). The lower boundary may be chosen as 0, 32, 64, 96, 128, 160, etc. The upper boundary of the

buffer is then the lower boundary plus 23.

The address pointer is not required to start at the lower address boundary and may begin anywhere within

the defined modulo address range. In fact, the location of Rn determines the lower and upper boundaries.