Motorola DSP96002 - Manual (Page 808)

26 MOTOROLA
1. Send command WRITE PDB REGISTER and GO (no EX).
(ODEC selects PDB as destination for serial data.)
2. ACK
3. Send the 32-bit opcode: “ORI #$10, OMR”
(After the 32 bits have been received, the PDB register drives the PDB. ODEC releases the chip
from “halt” state and the ORI instruction is executed. This instruction sets the “CE” bit in the
OMR register. The signal that marks the end of the instruction returns the chip to the “halt” state
and an acknowledge is issued to the command controller.)
4. ACK
Only now can we read the valid-bits using the HIT/MISS mechanism as described in sec-
tion 5.2.
To switch back to the PRAM mode, the same sequence is preformed, but this time using
“ANDI #$ef, OMR”.
5.4.4 Synchronous Start of the Execution of Multiple Chips
This routine will load each processor with the information necessary for starting the exe-
cution of its program and in the end will synchronously release all the processors from the
Debug Mode.
1. The command controller selects the first processor.
2. Send command WRITE PDB REGISTER (no GO, no EX).
(ODEC selects PDB as destination for serial data.)
3. ACK
4. Send 32 bits of the opcode of a two word jump instruction ($030c3f80).
(After all the 32-bits have been received the PDB register drives the PDB. ODEC causes the
core to load the opcode. An acknowledge is issued to the command controller.)
5. ACK
6. Send command WRITE PDB REGISTER (no GO, no EX).
(ODEC selects PDB as destination for serial data.)
7. ACK
8. Send 32 bits of the target absolute address for the first processor ($xxxxxxxx)
9. ACK
10. The command controller selects the second processor.
11. Send command WRITE PDB REGISTER (no GO, no EX).
(ODEC selects PDB as destination for serial data.)
12. ACK
13. Send 32 bits of the opcode of a two word jump instruction ($030c3f80).
(After all the 32-bits have been received the PDB register drives the PDB. ODEC causes the
core to load the opcode. An acknowledge is issued to the command controller.)
14. ACK