Motorola DSP96002 - Manual (Page 439)

MOTOROLA DSP96002 USER’S MANUAL A - 251
IFcc.U Integer iF IFcc.U
Conditional Instruction
with CCR, ER, and IER Update
Operation:
If cc, then opcode operation
S
→
D
Assembler Syntax:
Opcode-Operands S,D IFcc.U
IFcc.U
Description:
If the specified integer condition is true, transfer data from the specified source S to the specified destina-
tion D. Also, store result(s) of the specified Data ALU operation and update the CCR, ER and IER regis-
ters with the status information generated by the Data ALU operation. If the specified condition is false,
no destinations are altered and the status register is not affected. The UNCC bit in the ER register is never
updated by the Data ALU operation. If no register move is specified, this instruction is assembled with a
R0 to R0 move.
"cc" may specify the following conditions:
Mnemonic Condition
CC (HS) - carry clear (higher or same) C = 0
CS (LO) - carry set (lower) C = 1
EQ - equal Z = 1
GE - greater or equal N && V = 0
GT - greater than Z v (N && V) = 0
HI - higher Z v C = 0
LE - less or equal Z v (N && V) = 1
LS - lower or same Z v C = 1
LT - less than N && V = 1
MI - minus N = 1
NE(Q) - not equal Z = 0
PL - plus N = 0
VC - overflow clear V = 0
VS - overflow set V = 1
AL - always true n.a.
CAUTION
See restrictions in Section A.10.6 concerning Rn, Mn, and Nn registers as a
destination.
Move Move