Motorola DSP96002 - Manual (Page 172)

10 - 6 DSP96002 USER’S MANUAL MOTOROLA
10.3.4.5 Trace Mode Enable (TME) Bit 8
This control bit, when set, enables the Trace Mode causing the chip to enter the Debug Mode whenever the
execution of an instruction is completed and the Trace Counter is zero. This bit is cleared on hardware reset.
10.3.4.6 Reserved (Bits 9-15, 20-31)
These bits are reserved for future use. They are read as zero and should be written as zero for future com-
patibility.
10.3.4.7 Program Memory Breakpoint Occurrence (PBO) Bit 16
This read only status bit is set when a program memory breakpoint occurs. It is used by the external com-
mand controller to determine how the Debug Mode was entered. This bit is cleared on hardware reset and
when the OSCR is read.
10.3.4.8 Data Memory Breakpoint Occurrence (DBO) Bit 17
This read only status bit is set when a data memory breakpoint occurs. It is used by the external command
controller to determine how the debug mode was entered. This bit is cleared on hardware reset and when
the OSCR is read.
10.3.4.9 Trace Occurrence (TO) Bit 18
This read only status bit is set when the debug mode of operation is entered from a decrement to zero of
the trace counter and the trace mode has been armed. This bit is cleared on hardware reset and when the
OSCR is read.
10.3.4.10 Software Debug Occurrence (SWO) Bit 19
This status bit is set when the debug mode of operation is entered due to the execution of the (F)DEBUGcc
instruction with condition true. This bit is cleared on hardware reset and when the OSCR is read.
10.4 OnCE

HARDWARE BREAKPOINT LOGIC
Hardware breakpoints may be set on program memory or data memory locations. Also, the breakpoint does
not have to be in the program flow but within an approximate address range of where the program may be
executing. This significantly increases the programmer’s ability to monitor what the program is doing real-
time (see Section 10-3.4 for programming details).
The breakpoint logic has two identical sections: one for program memory breakpoints and one for data
memory breakpoints. Each section contains latches for core or DMA addresses, registers that store the up-
per and lower address limit, comparators and a counter. Figure 10-4 illustrates a block diagram of the
OnCE

Program Memory Breakpoint Logic and Figure 10-5 illustrates a block diagram of the OnCE

Data
Memory Breakpoint Logic.
10.4.1 Address Comparator Breakpoint Registers
Address comparators are useful in determining where a program may be getting lost or when data is being
written to areas that should not be written to in real-time. They are also useful in halting a program at a spe-