Motorola DSP96002 - Manual (Page 25)

3 - 2 DSP96002 USER’S MANUAL MOTOROLA
Figure 3-1. DSP96002 Block Diagram
3.2.2 Address Buses
Addresses are specified for internal X Data Memory and Y Data Memory on two unidirectional 32-bit buses,
X Address Bus (XAB) and Y Address Bus (YAB). Internal address bus sizes depend on the amount of in-
ternal memory implemented. External memory spaces for each port, A and B, are addressed via a single
32-bit unidirectional address bus driven by a three input multiplexer that can select the X Address Bus
(XAB), the Y Address Bus (YAB) or the Program Address Bus (PAB). On-chip peripherals and the DMA
Controller are memory mapped in the internal X memory space. When zero wait state external memory is
used, one instruction cycle is needed for each external memory access.
The XAB, YAB and PAB are dual access buses in the sense that one instruction cycle contains two slots,
the one slot is dedicated to the on-chip DMA transfers and the second is used for the core transfers.