Motorola DSP96002 - Manual (Page 91)

MOTOROLA DSP96002 USER’S MANUAL 7 - 5
external memory may use a fast access mode (page, static column, nibble or serial shift) during the current
bus cycle. The page circuit must be programmed with the characteristics of the external memory which allow
fast access modes. When the external memory cannot use a fast access mode in the current bus cycle,
—
T
–
T remains deasserted.
The page circuit selectively compares the address, memory space selection and bus mastership of a pre-
viously latched bus cycle C’ to the same attributes of the current bus cycle C based on the memory param-
eters programmed by the user in the Bus Control Register. Note that the previously latched bus cycle C’
may not be immediately prior to the current bus cycle, depending on the memory space mapping. The at-
tributes of the current and previous bus cycle are defined in Figure 7-2, and the page circuit programming
parameters are defined in Figure 7-3. These parameters (or functional equivalents) are user programmable
in the Bus Control Register. Hardware, software, or page circuit personal reset (generated when PE, XE,
and YE are clear) will reset the page circuit.
Once the memory parameters are programmed in the page circuit, the
—
T
–
T pin will provide information
about the current external bus cycle based on information latched in the page circuit about a previous ex-
ternal bus cycle. The page circuit is capable of detecting the following faults:
Page Fault -
—
T
–
T is deasserted if the current address A is not in the same memory page as the latched
address A’. The page size for the random access port of a DRAM or VRAM is typically the number
of rows. The page size parameter P is equal to the number of row address lines latched into the mem-
ory when the row address strobe is asserted. Typical page sizes for page or static column mode
RAMs are 256, 1024, etc. The page size for nibble mode RAMs is 4.
C C’ Bus Access Attributes
A A’ Address A0-A31
S S’ Space Select S0-S1
M M’ Bus Mastership
—
B
–
A
Figure 7-2. Bus Access Attributes
Name Memory Parameter Random Port(D/VRAM) Serial Port (VRAM)
P3-P0 Log2(page size) number of rows serial reg. size
(4 if nibble mode)
NS Non-Sequential Fault yes if nibble mode yes
MF Bus Mastership Fault depends on system depends on system
SF1 Memory Space Fault 1 depends on system depends on system
SF0 Memory Space Fault 0 depends on system depends on system
PE P Space Enable depends on system depends on system
XE X Space Enable depends on system depends on system
YE Y Space Enable depends on system depends on system
Figure 7-3. Page Circuit Programming Parameters