Motorola DSP96002 - Manual (Page 10)

MOTOROLA DSP96002 USER’S MANUAL 2 - 7
an "early write" signal for DRAM interfacing. R/
—
W is high for a read access and is low
for a write access. The R/
—
W pin is also the Host Interface read/write input. As an in-
put, R/
—
W may change asynchronous relative to the input clock. R/
—
W goes high if
the external bus is not used during an instruction cycle. R/
—
W is three-stated during
hardware reset.
—
B
–
S (Bus Strobe) - three-state, active low output when a bus master, three-stated when not
a bus master. Asserted at the start of a bus cycle (providing an "early bus start" signal
for DRAM interfacing) and deasserted at the end of the bus cycle. The early negation
provides an "early bus end" signal useful for external bus control. If the external bus is
not used during an instruction cycle,
—
B
–
S remains deasserted until the next external
bus cycle.
—
B
–
S is three-stated during hardware reset.
—
T
–
T (Transfer Type) - three-state, active low output when a bus master, three-stated when
not a bus master. When a bus master,
—
T
–
T is controlled by an on-chip page circuit
(see Section seven).
—
T
–
T is asserted when a fast access memory mode (page, static
column, nibble or serial shift register) is detected. If the external bus is not used during
an instruction cycle or a fault is detected by the page circuit during an external access,
—
T
–
T remains deasserted. The parameters of the page circuit fault detection are user
programmable.
—
T
–
T is three-stated during hardware reset.
—
T
–
S (Transfer Strobe) - three-state, active low output when a bus master, active low input
when not a bus master. When a bus master,
—
T
–
S is asserted to indicate that the ad-
dress lines A0-A31, S1, S0,
—
B
–
S,
—
B
–
L and R/
—
W are stable and that a bus read or
bus write transfer is taking place. During a read cycle, input data is latched inside the
DSP96002 on the rising edge of
—
T
–
S. During a write cycle, output data is placed on
the data bus after
—
T
–
S is asserted. Therefore
—
T
–
S can be used as an output enable
control for external data bus buffers if they are present. If the external bus is not used
during an instruction cycle,
—
T
–
S remains deasserted until the next external bus cycle.
An external flip-flop can delay
—
T
–
S if required for slow devices or more address de-
coding time. The
—
T
–
S pin is also the Host Interface transfer strobe input used to en-
able the data bus output drivers during host read operations and to latch data inside the
Host Interface during host write operations. As an input,
—
T
–
S may change asynchro-
nous relative to the input clock. Write data is latched inside the Host Interface on the
rising edge of
—
T
–
S.
—
T
–
S is three-stated during hardware reset.