Motorola DSP96002 User Manual
Page 831
MOTOROLA
49
Each requesting device input is first individually ANDed with its respective mask bit
(M0,M1,etc) and then all AND outputs are ORed together. The OR output goes to the
edge-triggered latch whose output initiates the DMA transfer. If an input is unmasked,
asserting that input will set the latch and initiate a DMA transfer. The DMA state machine
clears the latch when accessing the DMA source address. If more than one requesting
device input is enabled, the first edge on any input is latched and triggers a DMA transfer,
and any other edge that appears before the latch is cleared will be ignored.
Table 3 DMA Request Mask Bits
DMA
Request
Mask Bit
Requesting Device
M0
External (IRQA pin)
M1
External (IRQB pin)
M2
External (IRQC pin)
M3
Port A Host Receive Data (HRDF=1)
M4
Port A Host Transmit Data (HTDE=1)
M5
Port B Host Receive Data (HRDF=1)
M6
Port B Host Transmit Data (HTDE=1
)
M7
Timer 0 (TS=1)
M8
Timer 1 (TS=1)