Motorola DSP96002 - Manual (Page 501)

MOTOROLA DSP96002 USER’S MANUAL A - 313
A.9 INSTRUCTION TIMING
Figure A-7 shows the number of words and the number of clock cycles required for instruction execution.
The symbols used reference other tables to complete the instruction word and cycle count. The number
of words per instruction is dependent on the addressing mode and the type of parallel data bus move op-
eration specified. The number of execution clock cycles per instruction is dependent on many factors, in-
cluding the number of words per instruction, the addressing mode, whether the instruction fetch pipe is full
or not, whether the Data ALU is operating in the IEEE mode, the number of external bus accesses and
the number of wait states inserted in each external access. The following tables assume:
1. All instruction cycles are counted in clock oscillator cycles.
2. The instruction fetch pipeline is full.
3. There is no contention for instruction fetches.
4. There are no wait states for instruction fetches done sequentially (as for non-change-of-flow in-
structions), but they are taken into account for branch instructions (JMP, Jcc, RTI, etc.).
Mnemonic Words Cycles
ABS 1 + mv 2 + mv
ADD 1 + mv 2 + mv
ADDC 1 + mv 2 + mv
AND 1 + mv 2 + mv
ANDC 1 + mv 2 + mv
ANDI 1 2
ASL 1 + mv 2 + mv
ASL #shift 1 2
ASR 1 + mv 2 + mv
ASR #shift 1 2
Bcc 1 + ea 6 + jx
BCHG 1 + ea 4 + mvb
BCLR 1 + ea 4 + mvb
BFIND 1 + mv 2 + mv
BRA 1 + ea 6 + jx
BRCLR 2 8 + jx
BRSET 2 8 + jx
Mnemonic Words Cycles
Figure A-7 Instruction Timing Summary