Motorola DSP96002 - Manual (Page 764)

D-12 DSP96002 USER’S MANUAL MOTOROLA
Figure D-10b. Automatic Format Conversion – Double Precision
63 62 52 51 0
S Fraction
21 20
E
63 62 52 51 0
S Fraction
21 22
E
95 94 75 74 64 63 62 32 31 11 10 0
S E 0 Fraction i
L Data Memory
L Data Memory
i = 1 when normalized
i = 0 when unnormalized
*
* – Bits 11-31 (in Dn) or 0-20
(in L memory) are zero when
the register contains an SEP
result.
Dn
remaining 3 bits of the destination’s exponent are set if the number is an NaN or infinity, otherwise they are
the inverted MSB of the source’s exponent. Inverting the MSB effectively changes the bias from 127 to
1023.
When moving single precision numbers from the data ALU to memory, the above process is reversed, as
shown in Figure 10-a. The 23 most significant bits of the fraction are moved to the 23 fraction bits of the
destination. Note that the contents of the data ALU register may have more than 23 fractional bits if it was
the result of a previous DP move or SEP arithmetic operation; in this case, the fraction is simply truncated.
The MSB of the 11-bit exponent of the source in the data ALU is moved to the MSB of the exponent of the
destination. The 7 LSBs of the exponent of the source are copied to the seven LSBs of the exponent of the
source. Note that if the source was not a SP number (result of a DP move or a SEP arithmetic operation),
an incorrect exponent may be moved. Therefore, care must be taken to always round results to SP before
moving them to memory as single precision numbers.
When moving DP numbers from memory, the 52 bit fraction of the source is moved to the 52 bit fraction of
the destination, and the implicit integer bit is made explicit. If the number is denormalized, the V tag is set.
Again, extra cycles may be required when a denormalized number is used as an operand, depending on
the FZ bit in the SR. The 11-bit exponent of the source is copied to the 11-bit exponent of the destination.
When moving DP numbers from the data ALU to memory, the above process is reversed, as shown in Fig-