Motorola DSP96002 - Manual (Page 465)

MOTOROLA DSP96002 USER’S MANUAL A - 277
MPYS Signed Multiply MPYS
Operation:
S1.L * S2.L
→
D.M:D.L (parallel data bus move)
Assembler Syntax:
MPYS S1,S2,D
( See the MOVE instruction description.)
MPYS S2,S1,D
( See the MOVE instruction description.)
Description:
Multiply two signed operands and store the product in the specified destination register. The two source
operands are 32-bit integers and are taken from the low portion of S1 and S2. The result is a 64-bit signed
integer stored in the middle and low portions of D. Registers D8 and D9 can be used as source registers.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 64-bit integer.
CCR Condition Codes:
C - Not affected.
V - Cleared if the most significant 32 bits of the 64-bit result are the sign extension of
the least significant 32 bits. Set otherwise.
Z - Set if result is zero. Cleared otherwise.
N - Set if result is negative. Cleared otherwise.
I - Not affected.
LR - Not affected.
–
R - Not affected.
A - Not affected.
ER Status Bits: Not affected.