Motorola DSP96002 - Manual (Page 15)

2 - 12 DSP96002 USER’S MANUAL MOTOROLA
—
B
–
L (Bus Lock) - active low output, never three-stated. Asserted at the start of an external
indivisible Read-Modify-Write (RMW) bus cycle (providing an "early bus start" signal for
DRAM interfacing) and deasserted at the end of the write bus cycle.
—
B
–
L remains as-
serted between the read and write bus cycles of the RMW bus sequence.
—
B
–
L can
be used to indicate that special memory timing (such as RMW timing for DRAMs) may
be used or to "resource lock" an external multi-port memory for secure semaphore up-
dates. The early negation provides an "early bus end" signal useful for external bus con-
trol. If the external bus is not used during an instruction cycle,
—
B
–
L remains deassert-
ed until the next external indivisible RMW bus cycle.
—
B
–
L also remains deasserted if
the external bus cycle is not an indivisible RMW bus cycle or if there is an internal RMW
bus cycle. The only instructions which automatically assert
—
B
–
L are a BSET, BCLR
or BCHG instruction which accesses external memory.
—
B
–
L can also be asserted by
setting the LH bit in the BCR register (see Section seven).
—
B
–
L is deasserted during
hardware reset.
2.1.6 Reserved Pins
There are 5 spare pins reserved for future use.
2.2 BUS OPERATION
The external bus timing is defined by the operation of the Address Bus, Data Bus and Bus Control pins
described in paragraph 2.1.5. The DSP96002 external ports are designed to interface with a wide variety
of memory and peripheral devices, high speed static RAMs, dynamic RAMs and video RAMs as well as
slower memory devices. External bus timing is controlled by the
—
T
–
A control signal and by the Bus Con-
trol Registers (BCR) which are described in Section seven. The BCR and
—
T
–
A control the timing of the
bus interface signals. Insertion of wait states is controlled by the BCR to provide constant bus access tim-
ing, and by
—
T
–
A to provide dynamic bus access timing. The number of wait states is determined by the
—
T
–
A input or by the BCR, whichever is longer.
2.2.1 Synchronous Bus Operation
Synchronous external bus cycle consists of at least 4 internal clock phases. See the DSP96002 Technical
Data Sheet (DSP96002/D) for the specification of the internal clock phases. Each synchronous external
memory access requires the following procedure:
3:3. The external memory address is defined by the Address Bus A0-A31 and the Memory Ref-
erence Select signals S1 and S0. These signals change in the first phase of the external bus
cycle. The Memory Reference Select signals have the same timing as the Address Bus and
may be used as additional address lines. The Address and Memory Reference signals are
also used to generate chip select signals for the appropriate memory chips. These chip se-
lect signals change the memory chips from low power standby mode to active mode and be-
gin the read access time. This allows slower memories to be used since the chip select sig-
nals are address-based rather than read or write enable-based.