Motorola DSP96002 - Manual (Page 106)

7 - 20 DSP96002 USER’S MANUAL MOTOROLA
7.4.8.6 HCR Host Reset (HRES) Bit 5
The Host Reset (HRES) bit is used to reset the status bits of the HI and to initialize the transmit/receive paths
to the same state produced by hardware or software reset. The HOST reset (Host Interface personal reset)
is generated when HRES is set. The Host Interface exits the HOST reset state after this bit is cleared. HRES
is set by HW/SW reset.
7.4.8.7 HCR Reserved bits (Bits 6, 7, 14-31)
These reserved bits read as zero and should be written with zero for future compatibility.
7.4.8.8 HCR Host P Memory Read Interrupt Enable (HPRE) Bit 8
The Host P Memory Read Interrupt Enable (HPRE) bit is used to enable the P Memory Read interrupt when
the Host P Memory Read Command Pending (HPRP) status bit in the Host Status Register (HSR) is set.
When HPRE is cleared, HPRP interrupts are disabled. When HPRE is set, the Host P Memory Read inter-
rupt request will occur if HPRP is set. The starting address of this interrupt is shown in Figure 7-13. HPRE
is cleared by HW/SW reset.
7.4.8.9 HCR Host P Memory Write Interrupt Enable (HPWE) Bit 9
The Host P Memory Write Interrupt Enable (HPWE) bit is used to enable the P Memory Write interrupt when
the Host P Memory Write Command Pending (HPWP) status bit in the Host Status Register (HSR) is set.
When HPWE is cleared, HPWP interrupts are disabled. When HPWE is set, the Host P Memory Write in-
terrupt request will occur if HPWP is set. The starting address of this interrupt is shown in Figure 7-13.
HPWE is cleared by HW/SW reset.
7.4.8.10 HCR Host X Memory Read Interrupt Enable (HXRE) Bit 10
The Host X Memory Read Interrupt Enable (HXRE) bit is used to enable the X Memory Read interrupt when
the Host X Memory Read Command Pending (HXRP) status bit in the Host Status Register (HSR) is set.
When HXRE is cleared, HXRP interrupts are disabled. When HXRE is set, the Host X Memory Read inter-
rupt request will occur if HXRP is set. The starting address of this interrupt is shown in Figure 7-13. HXRE
is cleared by HW/SW reset.
7.4.8.11 HCR Host X Memory Write Interrupt Enable (HXWE) Bit 11
The Host X Memory Write Interrupt Enable (HXWE) bit is used to enable the X Memory Write interrupt when
the Host X Memory Write Command Pending (HXWP) status bit in the Host Status Register (HSR) is set.
When HXWE is cleared, HXWP interrupts are disabled. When HXWE is set, the Host X Memory Write in-
terrupt request will occur if HXWP is set. The starting address of this interrupt is shown in Figure 7-13.
HXWE is cleared by HW/SW reset.
7.4.8.12 HCR Host Y Memory Read Interrupt Enable (HYRE) Bit 12
The Host Y Memory Read Interrupt Enable (HYRE) bit is used to enable the Y Memory Read interrupt when
the Host Y Memory Read Command Pending (HYRP) status bit in the Host Status Register (HSR) is set.
When HYRE is cleared, HYRP interrupts are disabled. When HYRE is set, the Host Y Memory Read inter-