Motorola DSP96002 - Manual (Page 176)

10 - 10 DSP96002 USER’S MANUAL MOTOROLA
10.4.9 Data Memory Address Latch (ODAL)
The Data Memory Address Latch is a 32-bit register that latches the XAB or YAB on every cycle during the
core or DMA slot according to the DBS1-DBS0 bits in OSCR.
10.4.10 Data Memory Upper Limit Register (ODULR)
The Data Memory Upper Limit Register is a 32-bit register that stores the program memory breakpoint upper
limit. ODULR can only be read or written through the serial interface. Before enabling breakpoints, ODULR
must be loaded by the command controller.
10.4.11 Data Memory Lower Limit Register (ODLLR)
The Data Memory Lower Limit Register is a 32-bit register that stores the program memory breakpoint lower
limit. ODLLR can only be read or written through the serial interface. Before enabling breakpoints, ODLLR
must be loaded by the command controller.
10.4.12 Data Memory High Address Comparator (ODHC)
The Data Memory High Address Comparator compares the current data memory address (stored by ODAL)
with the ODULR contents. If ODULR is higher than or equal to ODAL then the comparator delivers a signal
indicating that the address is lower than or equal to the high limit.
10.4.13 Data Memory Low Address Comparator (ODLC)
The Data Memory Low Address Comparator compares the current data memory address (stored by ODAL)
with the ODLLR contents. If ODLLR is lower than or equal to ODAL then the comparator delivers a signal
indicating that address is higher than or equal to the low limit.
10.4.14 Data Memory Breakpoint Counter (ODBC)
The Data Memory Breakpoint Counter is a 32-bit counter which is loaded with a value equal to the number
of times minus one that a data memory address should be accessed before a breakpoint is acknowledged.
On each data memory access, the counter is decremented. When the counter has reached the value of zero
and a new occurrence takes place, a signal is generated and if the DBE bit is set, the chip will enter the
Debug Mode. ODBC can only be read or written through the serial interface. Before enabling Data Memory
Breakpoints, ODBC must be loaded by the command controller. Figure 10-5 illustrates a block diagram of
the Program Memory Breakpoint Counter logic.
10.5 TRACE/STEP MODE
To execute DSP96002 instructions in single or multiple steps, a special mode similar to the trace mode of
operation on the DSP56001 is necessary. The DSP96002 does not cause an interrupt exception as is the
case with the DSP56001 but enters the debug mode of operation instead and waits for further instructions
from the debug serial port after each instruction or group of instructions.
10.5.1 Trace Counter (OTC)
The trace mode has a 32-bit counter associated with it so that more than one instruction may be executed
before returning back to the debug mode of operation. The objective of the counter is to allow the user to
take multiple instruction steps real-time with no interference from the debug mode. This feature helps the