Mpyu unsigned multiply mpyu – Motorola DSP96002 User Manual
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DSP96002 USER’S MANUAL
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MPYU
Unsigned Multiply
MPYU
Operation:
S1.L * S2.L
→
D.M:D.L (parallel data bus move)
Assembler Syntax:
MPYU S1,S2,D
( See the MOVE instruction description.)
MPYU S2,S1,D
( See the MOVE instruction description.)
Description:
Multiply two unsigned operands and store the product in the specified destination register. The two source
operands are 32-bit integers and are taken from the low portion of S1 and S2. The result is a 64-bit un-
signed integer stored in the middle and low portions of D. Registers D8 and D9 can be used as source reg-
isters.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 64-bit integer.
CCR Condition Codes:
C
- Not affected.
V
- Cleared if the most significant 32 bits of the 64-bit result are zero. Set otherwise.
Z
- Set if result is zero. Cleared otherwise.
N
- Always cleared.
I
- Not affected.
LR
- Not affected.
–
R
- Not affected.
A
- Not affected.
ER Status Bits: Not affected.
IER Flags: Not affected.
Instruction Fields: