Motorola DSP96002 - Manual (Page 109)

MOTOROLA DSP96002 USER’S MANUAL 7 - 23
interrupt". HYRP is set when data is transferred from the TX register to the HRX register. HYRP is cleared
when the HTXC register is written by the DSP96002. HYRP is cleared by INIT (TREQ=1), HOST reset, and
HW/SW reset.
7.4.9.13 HSR Host Y Memory Write Command Pending (HYWP) Bit 13
The Host Y Memory Write Command Pending (HYWP) bit indicates that the HRX and TX registers contain
data from the host processor written by the host processor via the host function "TX register write and Y
Memory Write interrupt". HYWP is set when the host processor writes TX for the second time consecutively
using this host function. HYWP is cleared when the HRX register is read twice consecutively (once for ad-
dress and once for data) by the DSP96002. HYWP is cleared by INIT (TREQ=1), HOST reset, and HW/SW
reset.
7.4.10 Receive Register (RX) - Host Processor Side
This 32-bit register receives data from the Host Transmit Data register HTX. The RX register contains valid
data when the RXDF bit is set. The host processor may program the Receive Request Enable bit (RREQ),
to assert the Host Request
—
H
–
R pin when RXDF is set. This informs the host processor that the Receive
Registers RX is full. The RXDF bit is cleared by reading the RX register.
The RX register is viewed by the external host processor as an address in its memory map and may be read
by a host processor memory read operation. The RX register may also be read by an external DMA con-
troller (no A2-A5 address required) when the HI is in DMA mode (DMAE=1).
7.4.11 Transmit Register (TX) - Host Processor Side
This 32-bit register sends data to the Host Receive Data register HRX. The TX register contains valid data
when the TXDE bit is cleared. The TXDE bit is cleared by writing the TX register. The host processor may
program the Transmit Request Enable bit (TREQ) to assert the Host Request
—
H
–
R pin when TXDE is set.
This informs the host processor that the TX register is empty.
The Transmit Register (TX) is viewed by the external host processor as address in its memory map and
may be written by a host processor memory write operation. The TX register may also be written by an ex-
ternal DMA controller (no A2-A5 address required) when the HI is in DMA mode (DMAE=1).
7.4.12 Command Vector Register (CVR) - Host Processor Side
The 32-bit Host Command Vector Register (CVR) is used by the host processor to request a vectored ex-
ception service from the DSP96002. Any exception routine in the DSP96002 may be specified. The Host
Command feature is independent of any of the data transfer mechanisms in the HI.
7.4.12.1 CVR Host Vector (HV) Bits 0-7
The eight bit Host Vector (HV) specifies the Host Command exception address indirectly. When the Host
Command exception is recognized by the DSP96002 interrupt control logic, the starting address of the ex-
ception taken is 2*HV. This allows the host processor to change the exception starting address for the Host
Command exception. The host processor can select any of the 256 possible exception routine starting ad-
dresses in the DSP96002 by writing the exception routine starting address divided by 2 into HV. This means