Motorola DSP96002 - Manual (Page 14)

MOTOROLA DSP96002 USER’S MANUAL 2 - 11
(BSET, BCLR, BCHG) will not give up bus mastership until the end of the current instruc-
tion.
——
B
–
G is ignored during hardware reset.
—
B
–
A (Bus Acknowledge) - Open drain, active low output. When deasserting
—
B
–
A, the
DSP96002 drives
—
B
–
A high during half a CLK cycle and then disables the active pull-
up. In this way, only a weak external pull-up resistor is required to hold the line high.
—
B
–
A may be directly connected to
—
B
–
B in order to obtain the same functionality as the
MC68040
—
B
–
B pin. When
—
B
–
G is asserted, the DSP96002 becomes the pending
bus master. It waits until
—
B
–
B is negated by the previous bus master, indicating that
the previous bus master is off the bus. The pending bus master asserts
—
B
–
A to be-
come the current bus master.
—
B
–
A is asserted when the CPU or DMA has taken the
bus and is the bus master. While
—
B
–
A is asserted, the DSP96002 is the owner of the
bus (the bus master). When
—
B
–
A is negated, the DSP96002 is a bus slave.
—
B
–
A
may be used as a three-state enable control for external address, data and bus control
signal buffers.
—
B
–
A is three-stated during hardware reset.
Note that a current bus master may keep
—
B
–
A asserted after ceasing bus activity, re-
gardless of whether
—
B
–
R is asserted or deasserted. This is called "bus parking" and
allows the current bus master to use the bus repeatedly without re-arbitration until some
other device wants the bus.
The current bus master keeps
—
B
–
A asserted during indivisible read-modify-write bus
cycles, regardless of whether
—
B
–
G has been deasserted by the external bus arbitra-
tion unit. This form of "bus locking" allows the current bus master to perform atomic op-
erations on shared variables in multitasking and multiprocessor systems. Current in-
structions which perform indivisible read-modify-write bus cycles are BCLR, BCHG and
BSET.
—
B
–
B (Bus Busy) - active low input, must be asserted and deasserted synchronous to the input
clock (CLK) for proper operation.
—
B
–
B is deasserted when there is no bus master on
the external bus. In multiple DSP96002 systems, all
—
B
–
B inputs are tied together and
are driven by the logical AND of all
—
B
–
A outputs.
—
B
–
B is asserted by a pending bus
master (directly or indirectly by
—
B
–
A assertion) to indicate that it is now the current bus
master.
—
B
–
B is deasserted by the current bus master (directly or indirectly by
—
B
–
A
negation) to indicate that it is off the bus and is no longer the bus master. The pending
bus master monitors the
—
B
–
B signal until it is deasserted. Then the pending bus mas-
ter asserts
—
B
–
A to become the current bus master, which asserts
—
B
–
B directly or
indirectly.