Motorola DSP96002 - Manual (Page 170)

10 - 4 DSP96002 USER’S MANUAL MOTOROLA
Figure 10-2. OnCE

Controller and Serial Interface
been received), and two signals indicating that the core was halted and the DMA was halted. The ODEC
generates all the strobes required for reading and writing the selected OnCE

registers.
10.3.4 OnCE

Status and Control Register (OSCR)
The Status and Control Register is a 32-bit register used to select the events that will put the chip in Debug
Mode (see Figure 10-3). Breakpoints may be disabled or enabled on one or more memory spaces. The
Trace Mode of operation is also selected from OSCR. The control bits are read/write while the status bits
are read only.
10.3.4.1 Program Memory Breakpoint Enable (PBE0-PBE1) Bits 0-1
These control bits unmask program memory breakpoints allowing break-point interrupts to occur when a
program memory address is within the low and high program memory address registers and will select
whether the breakpoint will be recognized for read or write accesses. These bits are cleared on hardware
reset.
PBE1 PBE0 Selection
0 0 Breakpoint disabled
0 1 Breakpoint on write accesses
1 0 Breakpoint on read accesses
1 1 Breakpoint on both read and write accesses
10.3.4.2 Program Memory Breakpoint Selection (PBS0-PBS1) Bits 2-3
These control bits select whether the program memory breakpoints will be recognized on core program
memory fetches, core program memory accesses (MOVEM or MOVEP) or DMA program memory access-
es. These bits are cleared on hardware reset.