Motorola DSP96002 - Manual (Page 141)

MOTOROLA DSP96002 USER’S MANUAL 8 - 1
SECTION 8
EXCEPTION PROCESSING
8.1 INTRODUCTION
This section describes the actions of the DSP96002 which are outside the normal processing associated
with the execution of instructions. The sequence of actions taken by the DSP96002 on exception conditions
is described. Also, the interrupt priority level (IPL) of the processor and interrupt sources is described.
8.2 PROCESSING STATES
The DSP96002 is always in one of five processing states: normal, exception, reset, wait, or stop. The nor-
mal processing state is that associated with instruction execution.
8.2.1 Exception Processing State
The exception processing state is associated with interrupts. Exception processing may be internally gen-
erated by a software interrupt instruction, by an on-chip peripheral hardware interrupt, or by an error con-
dition. Externally, exception processing can be generated by an interrupt. Exception processing provides
an efficient context switch for servicing I/O devices.
8.2.2 Reset Processing State
The reset processing state is entered in response to the external
—
R
—
E
—
S
—
E
–
T pin being asserted.
Upon entering the reset state the following actions occur:
• Internal peripheral devices are reset and disabled.
• The modifier registers Mn are set to $FFFFFFFF.
• The Interrupt Priority Register (IPR) is cleared.
• All CCR, ER, IER and MR bits are cleared, except for I1 and I0 in the MR register.
• The interrupt mask bits I1,I0 in the MR register are set.
The DSP96002 remains in the reset state until
—
R
—
E
—
S
—
E
–
T is deasserted. Upon leaving the reset
state the chip operating mode bits of the operating mode register are loaded from the external Mode Select
pins (MODA, MODB, MODC) and program execution begins at the location described in Section 9.