Motorola DSP96002 - Manual (Page 147)

MOTOROLA DSP96002 USER’S MANUAL 8 - 7
Int ctl cyc1 i † i
*
Int ctl cyc2 i i
Fetch n3 n4 n5 n6 ii1 ii2 n7 n8 n9
Decode n2 REP NOP n4 n4 n5 n6 ii1 ii2 n7 n8
Execute n1 n2 REP NOP n4 n4 n5 n6 ii1 ii2 n7
i = interrupt
ii = interrupt instruction word
n = normal instruction word
n3 = REP #2 instruction
n4 = instruction being repeated twice
n5 = instruction that waits in the backup instruction latch
† interrupt rejected at this time
* interrupt can be reenabled at this time
Figure 8-5.
Example Of Interrupt Service When Interrupt Is Presented To REP Instruction
8.4 INTERRUPT SOURCES
Exceptions may originate from a number of interrupt sources. The DSP96002 interrupt sources are given
in Figure 8-6. The corresponding interrupt starting addresses for each interrupt source are shown. Inter-
rupt starting addresses are internally-generated 32-bit addresses which point to the starting address of the
fast interrupt service routine. The interrupt starting address for each interrupt is an address constant for
minimum overhead. Motorola reserves 128 interrupt starting address locations, while 128 locations are
reserved for user applications. These locations occupy the lowest 512 words of program memory space,
except for Hardware Reset, which may also occupy a location in the upper range of the program memory
address. If some of this space is not used, it may be used for program storage.
8.4.1 Internal Peripheral Interrupt Sources
The internal peripheral interrupt sources include all of the on-chip peripheral devices (Host and DMA).
Each internal interrupt source is level sensitive; i.e., each is serviced any time it is present and the interrupt
is not masked. Each internal hardware source has independent enable control.
8.4.2 Hardware RESET
The Hardware RESET interrupt is level sensitive and is the highest priority 3 interrupt. It is caused by as-
serting the
—
R
—
E
—
S
—
E
–
T pin.
8.4.3 External Interrupt Requests IRQA, IRQB and IRQC
The IRQA, IRQB and IRQC interrupts can be programmed to be level-sensitive or edge-sensitive. Level-
sensitive interrupts are not internally latched and are not automatically cleared when they are serviced; they
must be cleared by other means to prevent multiple interrupts. The edge-sensitive interrupts are latched as
pending on the high-to-low transition of the interrupt input and are automatically cleared when the interrupt
is serviced. IRQA, IRQB and IRQC can be programmed to one of three priority levels: level 0, 1, or 2, all of