Motorola DSP96002 User Manual

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DSP96002 USER’S MANUAL

MOTOROLA

CLK

No Wait State

Instruction

Two Wait State Instruction

ing hardware reset and becomes a level sensitive or negative edge triggered, maskable

interrupt request input during normal instruction processing. MODA, MODB and MODC

select one of 8 initial chip operating modes, latched into the operating mode register

(OMR) when the

—

–

T pin is deasserted. If

—

–

C is asserted syn-

chronous to the input clock (CLK), multiple processors can be resynchronized using the

WAIT instruction and asserting

—

–

C to exit the wait state.

2.1.3 Power and Clock (39 Pins)

CLK

(Clock Input) - active high input, high frequency processor clock. Frequency is twice the

instruction rate. An internal phase generator divides CLK into four phases (t0, t1, t2 and

t3) which is the basic instruction execution cycle. Additional tw phases are optionally

generated to insert wait states (WS) into instruction execution. A wait state is formed by

pairing a t2 and tw phase. CLK should be continuous with a 46-54% duty cycle.

Quiet VCC (4)

(Power) - isolated power for the CPU logic. Must be tied to all other chip power pins ex-

ternally. User must provide adequate external decoupling capacitors.

Quiet VSS (4)

(Ground) - isolated ground for the CPU logic. Must be tied to all other chip ground pins

externally. User must provide adequate external decoupling capacitors.

Address Bus VCC(4)

(Power) - isolated power for sections of address bus I/O drivers. Must be tied to

all other chip power pins externally. User must provide adequate external decoupling

capacitors.

Address Bus VSS(8)

(Ground) - isolated ground for sections of address bus I/O drivers. Must be tied

to all other chip ground pins externally. User must provide adequate external decoupling

capacitors.

Data Bus VCC(4)

(Power) - isolated power for sections of data bus I/O drivers. Must be tied to all

other chip power pins externally. User must provide adequate external decoupling ca-

pacitors.

Data Bus VSS(8)

(Ground) - isolated ground for sections of data bus I/O drivers. Must be tied to

all other chip ground pins externally. User must provide adequate external decoupling

capacitors.