Motorola DSP96002 - Manual (Page 248)

A - 60 DSP96002 USER’S MANUAL MOTOROLA
BSSET Branch to Subroutine if Bit Set
BSSET
Operation:
If S{n} = 1, then PC
→
SSH; SR
→
SSL;
PC + xxxx
→
PC
else PC + 1
→
PC
If S{n} = 1, then PC
→
SSH; SR
→
SSL;
PC + xxxx
→
PC
else PC + 1
→
PC
If S{n} = 1, then PC
→
SSH; SR
→
SSL;
PC + xxxx
→
PC
else PC + 1
→
PC
If S{n} = 1, then PC
→
SSH; SR
→
SSL;
PC + xxxx
→
PC
else PC + 1
→
PC
If S{n} = 1, then PC
→
SSH; SR
→
SSL;
PC + xxxx
→
PC
else PC + 1
→
PC
If S{n} = 1, then PC
→
SSH; SR
→
SSL;
PC + xxxx
→
PC
else PC + 1
→
PC
If S{n} = 1, then PC
→
SSH; SR
→
SSL;
PC + xxxx
→
PC
else PC + 1
→
PC
Assembler Syntax:
BSSET #bit,X: ea, label
BSSET #bit,X: aa, label
BSSET #bit,X: pp, label
BSSET #bit,Y: ea, label
BSSET #bit,Y: aa, label
BSSET #bit,Y: pp, label
BSSET #bit,S,label
Description:
The nth bit in the source operand is tested. If the tested bit is set, the address of the instruction immediately
following the BSSET instruction and the status register are pushed onto the stack. Program execution
then continues at location PC+displacement. The PC contains the address of the next instruction. If the
tested bit is cleared, the PC is incremented and program execution continues sequentially. However, the
address register specified in the effective address field is always updated independently of the condition.
The displacement is a 2’s complement 32-bit integer that represents the relative distance from the current
PC to the destination PC. The 32-bit displacement is contained in the extension word of the instruction.
All memory alterable addressing modes may be used to reference the source operand. Absolute Short,
I/O Short and Register Direct addressing modes may also be used. Note that if the specified source oper-
and S is the SSH, the stack pointer register will be decremented by one; if the condition is true, the push
operation will write over the stack level where the SSH value was taken. The bit to be tested is selected
by an immediate bit number 0-31. See Section A.10 for restrictions.
CCR Condition Codes: Not affected.
ER Status Bits: Not affected.
IER Flags: Not affected.
Instruction Fields: