Motorola DSP96002 - Manual (Page 470)

A - 282 DSP96002 USER’S MANUAL MOTOROLA
NEGC Negate with Carry NEGC
Instruction Fields:
(u u)
D d d d
Dn.L n n n where nnn = 0-7
Timing: 2 + mv oscillator clock cycles
Memory: 1 + mv program words
Operation:
0 - D.L - C
→
D.L (parallel data bus move)
Assembler Syntax:
NEGC D
( See the MOVE instruction description.)
Description:
Subtract the low portion of the destination operand D from zero along with the C bit of the condition code
register and store the result in the low portion of D. This instruction is useful when negating a multiple
precision number since it is not necessary to first zero an input operand as would be the case if the SUB
instruction were used. Note that the higher precision long words of the input variable must first be moved
to the lower portion of the Dn.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 32-bit integer.
CCR Condition Codes:
C - Set if a borrow is generated from the MSB of the result. Cleared otherwise.
V - Set if result overflows. Cleared otherwise.
Z - Cleared if the result is not zero. Unchanged otherwise.
N - Set if result is negative. Cleared otherwise.
I - Not affected.
LR - Not affected.
–
R - Not affected.
A - Not affected.
ER Status Bits: Not affected.
IER Flags: Not affected.
Instruction Format: NEGC D ( See the MOVE instruction description.)
10 0001 uu11 1ddd
31 14 13 0
OPTIONAL EFFECTIVE ADDRESS EXTENSION OR IMMEDIATE LONG DATA
DATA BUS MOVE FIELD