Motorola DSP96002 - Manual (Page 119)

MOTOROLA DSP96002 USER’S MANUAL 7 - 33
sors are used to transfer data without interfering with the local processing in both chips. Figure 7-17 contains
a diagram showing the data paths and control lines used for the data transfers.
A data write transfer is initiated when the slave’s
—
H
–
R signal is asserted, indicating that its HI TX register
is empty and ready to receive a data word from the master. The
—
H
–
R signal is connected to an
–
I
—
R
–
Q
pin in the master where this pin is defined as a DMA service request input. When
—
H
–
R is asserted, the
master DMA Controller transfers the data word from the master’s memory to an external address selecting
the TX register in the slave’s HI as destination. After TX is written (negating
—
H
–
R), the data is transferred
by the HI to the HRX register, setting HRDF and TXDE. Setting TXDE causes
—
H
–
R to be asserted if TREQ
is set. In the slave’s DMA Controller, HRDF is defined as a DMA service request signal. When HRDF is
asserted, the slave’s DMA Controller initiates a data transfer from HRX to the slave memory, completing the
data transfer.
7.4.19.2 Data Read Using The On-Chip DMA Controllers
This example outlines the steps that a DSP96002 bus master, behaving as host processor, transfers data
from a DSP96002 bus slave, thorough the slave’s HI. The on-chip DMA Controllers of both DSP96002 pro-
cessors are used to transfer data without interfering with the local processing in both chips. Figure 7-18 con-
tains a diagram showing the data paths and control lines used for the data transfers.
A data read transfer is initiated when the slave’s
—
H
–
R signal is asserted, indicating that its HI RX register
is full and the data is ready to be read by the master.
—
H
–
R is connected to an
–
I
—
R
–
Q pin in the master
DSP96002 Bus Master
DMA Source DSP96002 Bus Slave
DMA Destination
DMA Request
Bus Master
Write Bus Cycle
from Memory
—
I
—
R
–
Q
S1, S0
A0–A31
—
T
–
A
—
T
–
S
R/
—
W
space
address
data
V
cc
empty
slave
select
decode
—
H
–
R
—
H
–
S
—
H
–
A
A2–A5
—
T
–
S
R/
—
W
D0–D31
DMA Request
Host
→
Memory
DMA Transfer
Host Data Full
Figure 7-17. DSP96002 to DSP96002 Data Write
(HRDF=1)
Transmit Data
Empty (TXDE=1)