Motorola DSP96002 - Manual (Page 46)

MOTOROLA DSP96002 USER’S MANUAL 4 - 7
4.7.10 ER Divide-by-Zero (DZ) Bit 9
The DZ flag in the DSP96002 can be set by software as part ofo an FDIV routine. No single DSP96002 in-
struction can set the DZ flag. The DZ bit is cleared during processor reset and during all floating-point in-
structions.
4.7.11 ER Underflow (UNF) Bit 10
The underflow bit is set if a result of a floating-point operation is too small to be represented in a floating-
point data register (i. e., strictly between +2
Emin
). The test is done on the exponent before rounding. A de-
normalized result will set the UNF bit. The UNF bit is not affected by fixed point operations. The UNF bit is
cleared during processor reset.
4.7.12 ER Overflow (OVF) Bit 11
The overflow bit is set if a floating-point result is too large to be represented in a floating-point data register
with the specified rounding precision as a normalized result. The test is done on the exponent after round-
ing the mantissa (i. e., the result with its mantissa rounded > 1.0 x 2
Emax+1
). Depending on the rounding
mode and the sign of the result, a decision is made as to what the returned result will be. This returned result
is the final rounded result. For example, the largest positive SP result which does not set OVF is $7F7FFFFF
for all rounding modes. Note that a positive overflow of a finite number with round to minus infinity also re-
turns $7F7FFFFF but sets OVF (see Section C.1.5.1 – General for additional information on the rounding
modes) . The OVF bit is not affected by fixed point operations. The OVF bit is cleared during processor re-
set.
4.7.13 ER Operand Error (OPERR) Bit 12
The operand error bit is set if an operation has no mathematical interpretation for the given operands.
Examples of operations which set the OPERR bit are (+
∞
)+(-
∞
), 0
×∞
, and
√
—
-n. The OPERR bit is not
affected by fixed point operations. The OPERR bit is cleared during processor reset.
4.7.14 ER Signaling NaN (SNAN) Bit 13
The signaling NaN bit is set when a signaling NaN is involved in an arithmetic floating-point operation. For
example, “FABS.S D” where D is an SNaN will set the SNaN bit and return a quiet NaN. The SNAN bit is
not affected by fixed point operations. The SNAN bit is cleared during processor reset. One example of
where signaling NaN can be used is to give a known value to uninitialized memory which can be used to
flag the user.
4.7.15 ER Not-a-Number (NAN) Bit 14
The Not-a-Number bit is set if the result of a floating-point operation is a NaN. For example, the DSP96002
sets the NaN bit as the result of operations which set the OPERR bit (i. e., the default result of invalid oper-
ations). The NAN bit is not affected by fixed point operations but is affected by some conversion instructions.
For example, “INT D” where D is a NaN will return the fixed point value $FFFFFFFF and set the NaN bit.
The NAN bit is cleared during processor reset.