Motorola DSP96002 - Manual (Page 118)

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7.4.18 96002 Programmer Considerations
7.4.18.1 Reading Status Bits
HF1, HF0, HCP, HPRP, HPWP, HXRP, HXWP, HYRP, HYWP, HTDE, and HRDF status bits are set or
cleared by the host processor side of the HI. These bits are individually synchronized to the DSP96002
clock.
The only system problem with reading status is HF1 and HF0 if they are encoded as a pair, e.g. the four
combinations 00, 01, 10, and 11 each have significance. This is because there is a very small probability
that the DSP96002 will read the status bits that were synchronized during transition. The solution to this
potential problem is to read the bits twice for consensus.
7.4.19 DSP96002 to DSP96002 Data Transfers - Examples
This section presents examples showing the use of the HI and the on-chip DMA Controller for data transfers
between two DSP96002 processors. The bus master accesses the slave’s HI using regular memory refer-
ences. The slave’s HI registers are memory mapped into the bus master memory space. Note that the bus
master HI is not used and that the slave’s HI is not in the DMA Mode (DMAE=0).
7.4.19.1 Data Write Using The On-Chip DMA Controllers
This example outlines the steps that a DSP96002 bus master, behaving as host processor, transfers data
to a DSP96002 bus slave, thorough the slave’s HI. The on-chip DMA Controllers of both DSP96002 proces-