Motorola DSP96002 - Manual (Page 789)

MOTOROLA 7
Cache Enable (CE) bit. When the CE bit is cleared (0) the DSP96002 is in PRAM mode.
When the CE bit is set, the processor is in cache mode. The CE bit is cleared during reset.
2.5 NEW INSTRUCTIONS
The DSP96002 instruction set features six new instructions discussed in the following
paragraphs to support the instruction cache operation. APPENDIX A, starting on page 54,
presents a full description for each of the new instructions.
2.5.1 PLOCK ea
The PLOCK instruction locks the cache sector to which the specified effective address be-
longs. If the specified effective address does not belong to any cache sector, then the in-
struction will load the least recently used cache sector tag with the 25 most significant bits
of the specified address and then lock that cache sector. The instruction will update the
LRU stack accordingly.
All memory-alterable addressing modes may be used for the effective address, but a short
absolute address may not.
The PLOCK instruction is enabled only in cache mode. In PRAM mode it will cause an
illegal instruction trap to be taken.
2.5.2 PUNLOCK ea
The PUNLOCK instruction unlocks the cache sector to which the specified effective ad-
dress belongs. If the specified effective address does not belong to any cache sector, the
instruction will load the least recently used cache sector tag with the 25 most significant
bits of the specified address. The instruction will then update the LRU stack accordingly.
All memory-alterable addressing modes may be used for the effective address, but a short
absolute address may not.
The PUNLOCK instruction is enabled only in cache mode. In PRAM mode it will cause an
illegal instruction trap to be taken.
2.5.3 PLOCKR label or PLOCKR Rn
The PLOCKR instruction locks the cache sector to which the sum (PC + specified dis-
placement) belongs. If the sum does not belong to any cache sector, then the instruction
31 5 4 3 2 1 0
MA MB MC DE CE reserved
Cache Enable
SPM
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