Motorola DSP96002 - Manual (Page 62)

MOTOROLA DSP96002 USER’S MANUAL 5 - 9
• It has the same pattern for all precisions.
• All bits of the fraction are set to one.
• The biased exponent is set to all ones.
• The sign bit is cleared.
• In the internal floating-point format, the I bit is always set to one; note that if the I bit is set to
zero, the pattern is not recognized as a legal pattern by the Data ALU hardware, and opera-
tions on these bit patterns may yield unexpected results.
The IEEE specification defines the manner in which NaNs are handled when used as inputs to an operation.
If a SNaN is used as an input, it requires that a QNaN be returned as the result if traps are disabled, which
is the case for the DSP96002. The DSP96002 handles operations with SNaNs by generating the legal
QNaN as a result. If QNaNs are used as input, it requires that one of the input QNaNs be returned as a
result. The DSP96002 can only return the legal QNaN, and therefore, to be fully IEEE compatible, the only
QNaN that should be used is the legal QNaN.
5.5 AUTOMATIC FLOATING-POINT FORMAT CONVERSIONS
There are two kinds of automatic floating-point format conversions within the DSP96002:
1. Conversion of a floating-point operand in any memory data format to the double precision in-
ternal data format of a floating-point data register. This is done when moving data from an ex-
ternal (to the Data ALU) location into a Data ALU floating-point register.
2. Conversion of a floating-point operand in the internal data format of a floating-point data reg-
ister to any memory data format. This is done when moving data from a Data ALU floating-
point register to an external (to the Data ALU) location.
5.5.1 Conversion to the Double Precision Internal Data Format
Since the internal data format used by the DSP96002 Data ALU is double precision, all external floating-
point operands are converted to double precision values before writing them into a Data ALU floating-point
register. The conversion is actually a "bit rearranging" operation using the procedure shown in Figure 5-5.
When converting a single precision number to the internal register data format, the implicit bit is revealed
and stored as an explicit bit in the register. If the number to be converted is a denormalized single precision
floating-point number, the U tag will be set indicating an unnormalized number. If such a number is to be
used as an operand for floating-point operations, two cases arise depending on the state of the FZ (Flush-
to-Zero) bit in the SR. In the Flush-to-Zero mode, the operand will be considered as zero in calculations.
However, the data stored in the register will not be affected (unless the register is also the destination of
the current operation). In the IEEE mode, the operand will be first "corrected" by adding to the execution
cycle extra cycles for normalization. However, the data stored in the register will not be affected (unless
the register is also the destination of the current operation).
When converting a double precision number to the internal register data format, the implicit bit is revealed
and stored as an explicit bit in the register. If the number to be converted is a denormalized double preci-
sion (SEP in the DSP96002) floating-point number, the V tag will be set. If such a number is to be used as
an operand for floating-point operations, two cases arise depending on the state of the FZ (Flush-to-Zero)
bit in the SR. In the Flush-to-Zero mode, the operand will be considered as zero in calculations. However,
the data stored in the register will not be affected (unless the register is also the destination of the current
operation). In the IEEE mode, multiply operands will be first "wrapped" by adding to the execution cycle
extra cycles for normalization. However, the data stored in the register will not be affected (unless the