Motorola DSP96002 - Manual (Page 796)

14 MOTOROLA
to does), the content of that word is changed in the internal Program Memory. This should
be transparent to the user since, although the word content had been changed, it’s valid-
bit remains cleared as it was, and therefore the content is meaningless. Nevertheless, if
the user switches to PRAM mode without flushing the cache the new word content could
be meaningful.
2.10 DEFAULT MODE ON HARDWARE RESET
After reset, the DSP96002 configuration acts just as if there were no instruction cache fea-
ture available, and the three MOD pins determine the processor’s operating mode. All val-
id-bits are cleared. All cache sectors are in unlocked state. The tag registers values form
a contiguous 1K segment of memory and therefore hold the values 0,1,2,...,7 that corre-
spond to the PRAM addresses 0, 128, 256,... etc. The LRU stack holds a default descend-
ing order of sectors, so that sector number 0 is the most recently used and sector number
7 is the least recently used.
2.11 CACHE OBSERVABILITY THROUGH THE OnCE
The DSP96002 OnCE supports a fully non-intrusive system debug capability when the
processor is in cache mode. It allows the user to observe the cache status, showing which
memory sectors are currently mapped into cache sectors, which cache sectors are
locked, and which cache sector is the least recently used. Furthermore, the user can ob-
serve the values of the valid-bits for any cache location while the chip is in debug mode
by reading the tag registers’ contents, lock bits, LRU bits, and valid-bits serially through
the OnCE.
For more information, refer to Section 5 - OnCE ENHANCEMENTS.
2.12 RESTRICTIONS AND REMARKS
2.12.1 Change of OMR Bit 4 (Cache Enable bit)
The instruction which changes the value of OMR bit 4 should be followed by three NOPs
prior to the first instruction whose fetch will be executed in the new cache operating mode.
The use of NOPs is highly recommended. Although other instructions could be used, note
that the delay in the switch of cache operating mode will be three decoding cycles. For
example, a MOVE with predecrement addressing mode, followed by a single NOP will suf-
fice.
It is recommended that OMR bits 0, 1, and 2 not be changed in parallel with a change in
OMR bit 4 since they affect the bootstrap mode, which should not be used while the pro-
cessor is in cache mode. Therefore, it is recommended that the ORI and ANDI instructions