Motorola DSP96002 User Manual
Page 131
MOTOROLA
DSP96002 USER’S MANUAL
7 - 45
7.5.2 DMA Controller Programming Model
The registers comprising the DMA Controller are shown in Figure 7-25 and Figure 7-26.
DMA Source Modifier Register
DSM0
addr X:$FFFFFFDF
DMA Source Address Register
DSR0
addr X:$FFFFFFDE
DMA Source Offset Register
DSN0
addr X:$FFFFFFDD
DMA Destination Modifier Register
DDM0
addr X:$FFFFFFDB
DMA Destination Address Register
DDR0
addr X:$FFFFFFDA
DMA Destination Offset Register
DDN0
addr X:$FFFFFFD9
DMA Counter
DCO0
addr X:$FFFFFFDC
31 30 29 28 27 26 25 24 DMA Control/Status Register
DCS0
DE DIE * DTD * DTM1 DTM0 DMAP addr X:$FFFFFFD8
23 22 21 20 19 18 17 16
DCP * * * * * * *
15 14 13 12 11 10 9 8
* M6 M5 M4 M3 M2 M1 M0
7 6 5 4 3 2 1 0
* * DSS2 DSS1 DSS0 DDS2 DDS1 DDS0
Figure 7-25. DMA Controller Programming Model - Channel 0
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