Motorola DSP96002 User Manual

Page 198

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DSP96002 USER’S MANUAL

MOTOROLA

(Division by Zero) - Set if the dividend is a finite nonzero number and the divisor is zero. The
result will be a correctly signed infinity (generated by the exclusive OR of the signs of the source
operands). Cleared otherwise. The DZ bit is not affected by fixed point operations. The DZ bit
is cleared during processor reset.

UNF

(Underflow) - Set if tininess is detected, that is, set if an intermediate unrounded result of a float-
ing-point operation is too small to be represented in a floating-point data register with the se-
lected rounding precision as a normalized result. The UNF bit is not affected by fixed point op-
erations. The UNF bit is cleared during processor reset.

OVF

(Overflow) - Set if a rounded floating-point intermediate result is too large to be represented in
a floating-point data register with the selected rounding precision. If the result is greater than or

equal to |

max-1

| the OVF bit will be set; otherwise it will be cleared. The largest single preci-

sion IEEE floating-point number representable in memory is $7F7FFFFF. It is possible to set
OVF and have INX cleared if the overflow is exact. The OVF bit is not affected by fixed point
operations. The OVF bit is cleared during processor reset.

OPERR

(Operand Error) - Set if an operation has no mathematical interpretation for the given operands.
Cleared otherwise. The result will be a quiet NaN if the destination has a floating-point format.
Examples of operations which generate quiet NaNs and set the OPERR bit are (+

∞

)+(-

∞

), 0

×∞

and

√

—

-n. The OPERR bit is not affected by fixed point operations. The OPERR bit is cleared

during processor reset.

SNAN

(Signaling NaN) - Set when a signaling NaN is involved in an arithmetic floating-point operation.
Cleared otherwise. The result will be a non-signaling NaN obtained by setting the most signif-
icant fraction bit of the significand. The SNAN bit is not affected by fixed point operations. The
SNAN bit is cleared during processor reset.

NaN

(Not-a-Number) - Set if the result of a floating-point operation is a NaN. Cleared otherwise. The
NAN bit is not affected by fixed point operations but is affected by some conversion instructions.
The NAN bit is cleared during processor reset.

UNCC

(Unordered Condition) - Set if a non-aware floating-point conditional instruction (FBcc, FJcc,
FFcc, etc.) is executed when the NAN bit is set (the unordered condition). Not affected other-
wise. The UNCC bit is cleared during processor reset.

The

IEEE Standard 754-1985 for Binary Floating-Point Arithmetic

(754-standard) explicitly

specifies how to handle comparison operations when one or more of the operands is a NaN
(which the 754-standard created). However, a great deal of software has been written and some
is still being written, in an environment which is not aware of the NaN data type. In order to port
such software to an IEEE 754-1985 standard environment, a special bit, the unordered condition
code (UNCC) bit, was created in the DSP96002. This bit can be used when porting the software
to ensure that the intended branch is taken, or an exception is generated, when the ported pro-
gram processes a NaN.

Typically, branches are taken on predicates and their compliments assuming the operands can
be ordered (i. e., placed on the real number line). However, NaNs, by definition, do not have any
order relationship to numbers on the real number line. For example, when a FCMP is executed
the NaN bit in the ER will be set if either operand is a NaN. When a subsequent conditional in-
struction (e. g. FBGT) is executed, the UNCC bit in the ER will be set if the NaN bit in the ER
was set when the conditional branch instruction was executed. Because one of the operands
was a NaN, the branch will be failed. If the original author was "aware" of NaNs, then the deci-
sion may be wrong. In this case, it may be prudent to insert a FBERR instruction following the
conditional branch instruction in the failed path. This is because one of the error conditions that
the FBERR instruction detects is that the UNCC bit was set. The error handler will be aware of
NaNs and take corrective action.

It could be argued that the same result would be achieved by executing a Floating-Point Branch
on an unordered (FBUN) instruction instead of the FBERR instruction thereby eliminating the