Motorola DSP96002 - Manual (Page 158)

9 - 2 DSP96002 USER’S MANUAL MOTOROLA
9.1.2 Mode 1 (Internal PRAM enabled, Reset at $FFFFFFFE, Port B)
In Mode 1, the internal program memory occupies the lower portion of the program memory space. Ad-
dresses higher than the highest internal program memory location are directed to external program mem-
ory. The address of the hardware reset vector is $FFFFFFFE, located in the Port B external program mem-
ory space. The program memory map for this mode is shown in Figure 9-2.
9.1.3 Mode 2 (Internal PRAM disabled, Reset at $00000000, Port A)
In Mode 2 the internal program memory is disabled. All references to program memory space are directed
external program memory. The address of the hardware reset vector is $00000000, located in the Port A
external program memory space. The program memory map for this mode is shown in Figure 9-2.
9.1.4 Mode 3 (Internal PRAM disabled, Reset at $00000000, Port B)
In Mode 3 the internal program memory is disabled. All references to program memory space are directed
external program memory. The address of the hardware reset vector is $00000000, located in the Port B
external program memory space. The program memory map for this mode is shown in Figure 9-2.
9.1.5 Modes 4-7 (Bootstrap modes)
The bootstrap modes load the internal program memory from an external source. The type and location of
the source is selected according to the values of the MA and MB bits in the OMR. After loading the internal
program memory, the DSP96002 begins program execution at the address located at the on-chip program
memory address $00000000.
The bootstrap is implemented by executing a bootstrap program located in an user invisible bootstrap pro-
gram ROM which is mapped into the program memory space for the duration of the bootstrap operations.
When the chip exits the reset state in one of the bootstrap modes, the following actions occur:
1. On-chip hardware maps a 64 word by 32-bit, user invisible, ROM into the internal DSP96002
program memory space starting at location $00000000.
2. On-chip hardware makes the internal program RAM write-only for the duration of the bootstrap
load.
3. Program execution begins at location $00000000 of the internal bootstrap ROM. See Figure
9-3 for a listing of the DSP96002 Bootstrap program.
4. The bootstrap program reads OMR bits MA and MB to determine the bootstrap mode select-
ed.
In mode 4, the bootstrap program loads the internal program RAM from 4,096 consecutive byte-wide
external program memory locations starting at $FFFF0000 through Port A.
In mode 5, the bootstrap program loads the internal program RAM from 4,096 consecutive byte-wide
external program memory locations starting at $FFFF0000 through Port B.
In mode 6, the bootstrap program loads the internal program RAM from an external host processor
through the Host Interface in Port A. If the Host Interface flag HF1 is cleared, the bootstrap program
assumes that the external host processor is an 8-bit wide source which will supply up to 4,096 bytes.
If the Host Interface flag HF1 is set, the bootstrap program assumes that the external host processor
is a 32-bit wide source which will supply up to 1,024 32-bit words to load into the program RAM.
The external host processor may terminate the bootstrap program by setting the Host Interface flag
HF0.
In mode 7, the bootstrap program loads the internal program RAM from an external host processor
through the Host Interface in Port B. If the Host Interface flag HF1 is cleared, the bootstrap program
assumes that the external host processor is an 8-bit wide source which will supply up to 4,096 bytes.