Motorola DSP96002 - Manual (Page 263)

MOTOROLA DSP96002 USER’S MANUAL A - 75
"end-of-loop" processing begins.
When executing a DO loop, the instructions are actually fetched each time through the loop. Therefore, a
DO loop can be interrupted. DO loops can also be nested. When DO loops are nested, the end-of-loop ad-
dresses must also be nested and are not allowed to be equal. The assembler generates an error message
when DO loops are improperly nested. Nested DO loops are illustrated in the example.
NOTE: The assembler calculates the end-of-loop address to be loaded into LA (the absolute address
extension word) by evaluating the end-of-loop expression "expr" and subtracting one. This is done to ac-
commodate the case where the last word in the DO loop is a two-word instruction. Thus, the end-of-loop
expression "expr" in the source code must represent the address of the instruction after the last instruction
in the loop as shown in the example. This is in contrast to locating labels for instructions other than DO and
DOR. In this case the labels are located on the same line as the target.
During the "end-of-loop" processing, the loop flag (LF) from the lower portion (SSL) of SP is written into the
status register (SR), the contents of the loop address (LA) register are restored from the upper portion (SSH)
of (SP-1), the contents of the loop counter (LC) are restored from the lower portion (SSL) of (SP-1), and the
stack pointer (SP) is decremented by two. Instruction fetches now continue at the address of the instruction
following the last instruction in the DO loop. Note that LF is the only bit in the status register (SR) that is
restored after a hardware DO loop has been exited.
Note: The loop flag (LF) is cleared by a hardware reset.
Restrictions: The "end-of-loop" comparison previously described actually occurs at instruction fetch time.
That is, LA is being compared with PC when the instruction at LA-2 is being executed. Therefore, instruc-
tions which access the program controller registers and/or change program flow cannot be used in locations
LA-2, LA-1, or LA.
Proper DO loop operation is not guaranteed if an instruction starting at address LA-2, LA-1, or LA specifies
one of the program controller registers SR, SP, SSL, LA, LC, (implicitly) PC as a destination register.
Similarly, the SSH program controller register may not be specified as a source or destination register in
an instruction starting at address LA-2, LA-1, or LA. Additionally, the SSH register cannot be specified as
a source register in the DO instruction itself and LA cannot be used as a target for jumps to subroutine
(i.e., JSR, JScc, JSSET, or JSCLR to LA). A DO instruction cannot be repeated using the REP instruction.
The following instructions cannot begin at the indicated position(s) near the end of a DO loop:
At LA-2, LA-1 and LA:
DO
BCHG/BCLR/BSET LA, LC, SR, SP, SSH, or SSL
BTST SSH
JCLR/JSET/JSCLR/JSSET SSH
LEA to LA, LC, SR, SP, SSH, or SSL
LRA to LA, LC, SR, SP, SSH, or SSL
MOVEC/M/P/S from SSH
MOVEC/I/M/P/S to LA, LC, SR, SP, SSH, or SSL
ANDI MR
ORI MR
At LA:
any two word instruction
(F)Jcc, JMP, (F)JScc, JSR, (F)Bcc, BRA, (F)BScc, BSR,
LRA, REP, RESET, RTI, RTR, RTS, STOP, WAIT