Motorola DSP96002 - Manual (Page 175)

MOTOROLA DSP96002 USER’S MANUAL 10 - 9
provides a means of checking hot spots in program segments as well as peripheral or data memory access-
es.
Program hot spots may be statistically evaluated by setting the breakpoint counter to a value, setting a pro-
gram address in the program address comparator registers, passing control of the DSP96002 back to the
user program and checking to see if a breakpoint occurs after n iterations of the program memory access.
The breakpoint counter becomes a powerful tool when debugging real-time fast interrupt sequences such
as servicing an A/D or D/A converter or stopping after a specific number of host transfers have occurred.
The breakpoint counters are cleared by hardware reset.
10.4.3 Program Memory Address Latch (OPAL)
The Program Memory Address Latch is a 32-bit register that latches the PAB on every cycle during the core
slot or during the DMA slot according to the PBS1-PBS0 bits in OSCR.
10.4.4 Program Memory Upper Limit Register (OPULR)
The Program Memory Upper Limit Register is a 32-bit register that stores the program memory breakpoint
upper limit. OPULR can only be read or written through the serial interface. Before enabling breakpoints,
OPULR must be loaded by the command controller.
10.4.5 Program Memory Lower Limit Register (OPLLR)
The Program Memory Lower Limit Register is a 32-bit register that stores the program memory breakpoint
lower limit. OPLLR can only be read or written through the serial interface. Before enabling breakpoints,
OPLLR must be loaded by the command controller.
10.4.6 Program Memory High Address Comparator (OPHC)
The Program Memory High Address Comparator compares the current program memory address (stored
by OPAL) with the OPULR contents. If OPULR is higher or equal than OPAL then the comparator delivers
a signal indicating that the address is lower than or equal to the high limit.
10.4.7 Program Memory Low Address Comparator (OPLC)
The Program Memory Low Address Comparator compares the current program memory address (stored
by OPAL) with the OPLLR contents. If OPLLR is lower or equal than OPAL then the comparator delivers a
signal indicating that the address is higher than or equal to the low limit.
10.4.8 Program Memory Breakpoint Counter (OPBC)
The Program Memory Breakpoint Counter is a 32-bit counter which is loaded with a value equal to the num-
ber of times minus one that a program memory address should be accessed before a breakpoint is acknowl-
edged. On each occurrence of the program memory address access, the counter is decremented. When
the counter has reached the value of zero and a new occurrence takes place a signal is generated and if
PBE is set the chip will enter the Debug Mode. The OPBC can only be read or written through the serial
interface. Before enabling Program Memory Breakpoints, OPBC must be loaded by the command control-
ler. Figure 10-5 illustrates a block diagram of the Program Memory Breakpoint Counter logic.