Motorola DSP96002 - Manual (Page 34)

MOTOROLA DSP96002 USER’S MANUAL 3 - 11
3.4 AGU
The major components of the AGU are
• Address Register Files
• Offset Register Files
• Modifier Register Files
• Temporary Address Registers
• Modulo Arithmetic Units
• Address Output Multiplexers
A block diagram of the AGU is shown in Figure 3-3.
3.4.1 Address Register Files
Each of two Address Register Files consists of four 32-bit registers. The two files contain the address reg-
isters R0-R3 and R4-R7 respectively, which usually contain addresses used as pointers to memory. Each
register may be read or written by the Global Data Bus. High speed access to the XAB and YAB is required
to allow maximum access time for the internal and external X Data Memory, Y Data Memory, and Program
Memory. Each address register may be used as input to its associated modulo arithmetic unit for a register
update calculation. Each register may be written by the Global Data Bus or by the output of its respective
modulo arithmetic unit. The registers accessed by the Global Data Bus and the Modulo Arithmetic Unit are
not required to be the same. A separate write enable is provided for each register.
CAUTION
Due to pipelining, if an address register R is the destination of a MOVE instruction,
the new contents will not be available for use as a pointer until the second following
instruction.
3.4.2 Offset Register Files
Each of two Offset Register Files consists of four 32-bit registers. The two files contain the offset registers
N0-N3 and N4-N7 respectively, and usually hold offset values used to update address pointers but can hold
data. Each offset register may be read or written by the Global Data Bus. Each offset register is read when
the same number address register is read and used as input to its associated modulo arithmetic unit. A
read address selects the offset register to be read to the Modulo Arithmetic Unit during an instruction cycle.
The registers accessed by the Global Data Bus and the Modulo Arithmetic Unit are not required to be the
same. A separate write enable is provided for each register.
CAUTION
Due to pipelining, if an offset register N is the destination of a MOVE instruction, the
new contents will not be available for use in address calculations until the second fol-
lowing instruction.
3.4.3 Modifier Register Files
Each of two Modifier Register Files consists of four 32-bit registers. The two files contain the modifier reg-
isters M0-M3 and M4-M7 respectively, and usually specify the type of modification made to an address reg-