Motorola DSP96002 - Manual (Page 29)

3 - 6 DSP96002 USER’S MANUAL MOTOROLA
cessors, another DSP96002 or DMA hardware. The HI appears as a memory mapped peripheral occupy-
ing 16 words in the host processor address space. Separate transmit and receive data registers are double-
buffered to allow the DSP96002 and host processor to efficiently transfer data at high speed. Host proces-
sor communication with the HI is accomplished using standard Host processor data move instructions and
addressing modes. Handshake flags are provided for polled or interrupt-driven data transfers.
3.2.11.2 DMA Controller
The DMA Controller performs all the address storage and effective address calculations necessary to ad-
dress the DMA source and destination operands. The DMA controller operates in parallel with other chip
resources to minimize data or program transfers overhead. The DMA controller contains one Source Ad-
dress Register, one Source Offset Register, one Source Modifier Register, one Destination Address Reg-
ister, one Destination Offset Register and one Destination Modifier Register for each channel.
In addition there are two control registers per channel. The Transfer Count down counter, decremented af-
ter each transfer, contains the number of DMA transfers remaining to be done. The DMA Control/Status
Register controls the DMA activities and contains the DMA status. All DMA registers are mapped into the
X memory space. The AGU is shared by the DMA for the source and destination address calculations. The
DMA addressing modes are: linear, bit reversed and modulo. For more details see Section 7.5.
3.3 DATA ALU BLOCK DIAGRAM
The major components of the Data ALU are
• Data ALU Register File
• Multiply Unit
• Adder Unit
• Logic Unit
• Format Converter
• Divide and Square Root Unit
• Controller and Arbitrator
A block diagram of the Data ALU architecture is shown in Figure 3-2.
D0, D1, D2, D3, D4, D5, D6, D7, D8 and D9 are 96-bit registers which serve as the Data ALU general pur-
pose register file. Every register is divided into three portions: high, middle, and low, each 32-bits wide. The
registers may be treated as ten 96-bit registers Dn (Dn.H:Dn.M:Dn.L), n=0,1,..,9 for floating-point source
and/or destination operands. These floating point registers receive inputs from the Multiplier, the Adder,
and the Subtracter and supply a source data register of the same form. Most Data ALU floating-point op-
erations specify the 96-bit registers as source and/or destination operands. However, D8 and D9 are never
destinations of a Data ALU operation.
The data is stored in the registers in double precision floating-point format. Each register may be read or
written over the XDB or YDB as a floating-point operand. A format conversion is automatically performed
when a Dn register is written with an operand of a different floating-point format. This can occur when writ-
ing Dn from the XDB or YDB as a result of a single precision floating-point MOVE. If a single precision op-
erand is written to a floating point data register, the middle portion of the data register is written with the
mantissa portion of the word operand, the low portion is zeroed and the high portion is written with the ex-
ponent portion of the word operand.