Motorola DSP96002 - Manual (Page 189)

MOTOROLA DSP96002 USER’S MANUAL A - 1
APPENDIX A
INSTRUCTION SET DETAILS
A.1 INTRODUCTION
This appendix contains detailed information about each instruction defined in the DSP96002 instruction
set. They are arranged in alphabetical order.
A.2 ADDRESSING MODES
Addressing modes are categorized by the ways in which they may be used. The following classifications
will be used in the instruction definitions. Figure A-1 shows the various categories to which each address-
ing mode belongs.
Update (U) The addressing mode may be used to modify address registers without an associated
data move.
Parallel (P) The addressing mode may be used in instructions where two effective addresses are
required.
Memory (M) The addressing mode uses the effective addressing field and refers to operands in
memory.
Alterable (A) The addressing mode refers to alterable (writable) registers or memory.
These addressing mode categories may be combined so that additional, more restrictive classifications
may be defined. For example, the instruction descriptions may use a memory alterable classification. This
refers to addressing modes which are both memory addressing modes and alterable addressing modes.
Memory alterable addressing modes use the effective address to address memory and exclude the imme-
diate addressing mode and the long displacement addressing mode.
The address register indirect addressing modes require that the offset register number be the same as the
address register number. The assembler syntax "Nn" supports this future feature. The assembler syntax
"N" may be used instead of "Nn" in the address register indirect memory addressing modes. If "N" is spec-
ified, the offset register number is the same as the address register number.
A.2.1 Addressing Mode Modifiers
The addressing mode selected in the instruction word is further specified by the contents of the address
modifier register Mn. The addressing mode update modifiers are shown in Figure A-2. There are no re-
strictions on the use of modifier types with any memory addressing mode.