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DS3170 DS3/E3 Single-Chip Transceiver
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Figure 9-13. DS3 Frame Format................................................................................................................................ 81
Figure 9-14. DS3 Subframe Framer State Diagram .................................................................................................. 81
Figure 9-15. DS3 Multiframe Framer State Diagram................................................................................................. 82
Figure 9-16. G.751 E3 Frame Format ....................................................................................................................... 89
Figure 9-17. G.832 E3 Frame Format ....................................................................................................................... 92
Figure 9-18. MA Byte Format .................................................................................................................................... 92
Figure 9-19. HDLC Controller Block Diagram ........................................................................................................... 97
Figure 9-20. Trail Trace Controller Block Diagram .................................................................................................. 100
Figure 9-21. Trail Trace Byte (DT = Trail Trace Data)............................................................................................. 102
Figure 9-22. FEAC Controller Block Diagram.......................................................................................................... 103
Figure 9-23. FEAC Codeword Format.................................................................................................................... 104
Figure 9-24. Line Encoder/Decoder Block Diagram ................................................................................................ 105
Figure 9-25. B3ZS Signatures ................................................................................................................................. 107
Figure 9-26. HDB3 Signatures................................................................................................................................. 107
Figure 9-27. BERT Block Diagram .......................................................................................................................... 108
Figure 9-28. PRBS Synchronization State Diagram................................................................................................ 110
Figure 9-29. Repetitive Pattern Synchronization State Diagram............................................................................. 111
Figure 9-30. LIU Functional Diagram....................................................................................................................... 112
Figure 9-31. DS3/E3 LIU Block Diagram................................................................................................................. 113
Figure 9-32. Receiver Jitter Tolerance .................................................................................................................... 116
Figure 12-1. JTAG Block Diagram........................................................................................................................... 202
Figure 12-2. JTAG TAP Controller State Machine .................................................................................................. 203
Figure 12-3. JTAG Functional Timing...................................................................................................................... 207
Figure 13-1. DS3170 Pin Assignments—100-Ball CSBGA (Top View) .................................................................. 212
Figure 13-2. DS3170 Pin Assignments—100-Pin LQFP ......................................................................................... 212
Figure 14-1. Mechanical Dimensions—100-Ball CSBGA........................................................................................ 213
Figure 14-2. Mechanical Dimensions—100-Pin LQFP............................................................................................ 214
Figure 17-1. Clock Period and Duty Cycle Definitions............................................................................................. 218
Figure 17-2. Rise Time, Fall Time, and Jitter Definitions ........................................................................................ 218
Figure 17-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) .................................................................... 218
Figure 17-4. Hold, Setup, and Delay Definitions (Falling Clock Edge).................................................................... 219
Figure 17-5. To/From Hi Z Delay Definitions (Rising Clock Edge) .......................................................................... 219
Figure 17-6. To/From Hi Z Delay Definitions (Falling Clock Edge) ......................................................................... 219
Figure 17-7. SPI Interface Timing Diagram ............................................................................................................. 223
Figure 17-8. Micro Interface Nonmultiplexed Read/Write Cycle ............................................................................. 225
Figure 17-9. Micro Interface Multiplexed Read Cycle.............................................................................................. 226
Figure 17-10. DS3 Pulse Mask Template................................................................................................................ 228
Figure 17-11 E3 Waveform Template...................................................................................................................... 229
