Rainbow Electronics DS31256 User Manual
General description, Applications, Ordering information
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GENERAL DESCRIPTION
The DS31256 Envoy is a 256-channel HDLC
controller capable of handling up to 64 T1 or E1
data streams or two T3 data streams. Each of the
16 physical ports can handle one, two, or four
T1 or E1 data streams. The Envoy is composed
of the following blocks: Layer 1, HDLC
processing, FIFO, DMA, PCI bus, and local bus.
There are 16 HDLC engines (one for each port)
that are each capable of operating at speeds up
to 8.192Mbps in channelized mode and up to
10Mbps in unchannelized mode. The Envoy also
has three fast HDLC engines that only reside on
Ports 0, 1, and 2. They are capable of operating
at speeds up to 52Mbps.
APPLICATIONS
Channelized and Clear-Channel
(Unchannelized) T1/E1 and T3/E3
Routers with Multilink PPP Support
High-Density Frame-Relay Access
xDSL Access Multiplexers (DSLAMs)
Triple HSSI
High-Density V.35
SONET/SDH EOC/ECC Termination
ORDERING INFORMATION
PART TEMP
RANGE PIN-PACKAGE
DS31256
0°C to +70°C
256 PBGA
FEATURES
§ 256 Independent, Bidirectional HDLC
channels
§ Up to 132Mbps Full-Duplex Throughput
§ Supports Up to 64 T1 or E1 Data Streams
§ 16 Physical Ports (16 Tx and 16 Rx) That
Can Be Independently Configured for
Channelized or Unchannelized Operation
§ Three Fast (52Mbps) Ports; Other Ports
Capable of Speeds Up to 10Mbps
(Unchannelized)
§ Channelized Ports Can Each Handle One,
Two, or Four T1 or E1 Lines
§ Per-Channel DS0 Loopbacks in Both
Directions
§ Over-Subscription at the Port Level
§ Transparent Mode Supported
§ On-Board Bit Error-Rate Tester (BERT)
with Automatic Error Insertion Capability
§ BERT function Can Be Assigned to Any
HDLC Channel or Any Port
§ Large 16kB FIFO in Both Receive and
Transmit Directions
§ Efficient Scatter/Gather DMA Maximizes
Memory Efficiency
§ Receive Data Packets are Time-Stamped
§ Transmit Packet Priority Setting
§ V.54 Loopback Code Detector
§ Local Bus Allows for PCI Bridging or Local
Access
§ Intel or Motorola Bus Signals Supported
§ Backward Compatibility with DS3134
§ 33MHz 32-Bit PCI (V2.1) Interface
§ 3.3V Low-Power CMOS with 5V Tolerant
I/O
§ JTAG Support IEEE 1149.1
§ 256-Pin Plastic BGA (27mm x 27mm)
Features continued on page 6.
DS31256 Envoy
256-Channel, High-Throughput
HDLC Controller
www.maxim-ic.com
DEMO KIT AVAILABLE
Document Outline
- MAIN FEATURES
- DETAILED DESCRIPTION
- SIGNAL DESCRIPTION
- MEMORY MAP
- Introduction
- General Configuration Registers (0xx)
- Receive Port Registers (1xx)
- Transmit Port Registers (2xx)
- Channelized Port Registers (3xx)
- HDLC Registers (4xx)
- BERT Registers (5xx)
- Receive DMA Registers (7xx)
- Transmit DMA Registers (8xx)
- FIFO Registers (9xx)
- PCI Configuration Registers for Function 0 (PIDSEL/Axx)
- PCI Configuration Registers for Function 1 (PIDSEL/Bxx)
- GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT
- LAYER 1
- HDLC
- FIFO
- DMA
- PCI BUS
- LOCAL BUS
- JTAG
- AC CHARACTERISTICS
- MECHANICAL DIMENSIONS
- APPLICATIONS