Rainbow Electronics DS3170 - Manual (Page 171)

DS3170 DS3/E3 Single-Chip Transceiver
171 of 233
Register Name: TT.RSR
Register Description: Trail Trace Receive Status Register
Register Address: 0F4h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- -- RTIM RTIU RIDL
Bit 2: Receive Trail Trace Identifier Mismatch (RTIM)
0 = Received and expected trail trace identifiers match.
1 = Received and expected trail trace identifiers do not match; trail trace identifier
mismatch (TIM) declared.
Bit 1: Receive Trail Trace Identifier Unstable (RTIU)
0 = Received trail trace identifier is not unstable
1 = Received trail trace identifier is in an unstable condition (TIU); TIU is declared when eight
consecutive trail trace identifiers are received that do not match either the receive trail trace
identifier or the previously stored current trail trace identifier.
Bit 0: Receive Trail Trace Identifier Idle (RIDL)
0 = Received trail trace identifier is not in idle condition.
1 = Received trail trace identifier is in idle condition. Idle condition is declared upon the reception
of an all zeros trail trace identifier five consecutive times.
Register Name:
TT.RSRL
Register Description: Trail Trace Receive Status Register Latched
Register Address: 0F6h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- RTICL RTIML RTIUL RIDLL
Bit 3: Receive Trail Trace Identifier Change Latched (RTICL) – This bit is set when the receive trail trace
identifier is updated.
Bit 2: Receive Trail Trace Identifier Mismatch Latched (RTIML) – This bit is set when the TT.RSR.RTIM bit
transitions from 0 to 1.
Bit 1: Receive Trail Trace Identifier Unstable Latched (RTIUL) – This bit is set when the TT.RSR.RTIU bit
transitions from 0 to 1.
Bit 0: Receive Trail Trace Identifier Idle Latched (RIDLL) – This bit is set when the TT.RSR.RIDL bit transitions
from 0 to 1.