Rainbow Electronics DS3170 - Manual (Page 59)

DS3170 DS3/E3 Single-Chip Transceiver
59 of 233
Table 9-4. Source Selection of TCLKO (Internal Tx Clock)
SIGNAL
LOOPT
PORT.CR3
LBM[2:0]
( PORT.CR4 )
LIUEN
CLADC
( PORT.CR3 )
SOURCE
1 XXX 1 X Rx LIU
1 XXX 0 X RLCLK
0
PLB (011) 1 X Rx LIU
0 PLB (011) 0 X RLCLK
0 PLB disabled X 0 CLAD
TCLKO
0 PLB disabled X 1 TCLKI
Figure 9-3 shows the source of the RCLKO signals.
Figure 9-3. Internal Rx Clock
0
1
0
1
Rx LIU CLOCK
RLCLK
LIUEN
TCLKO
DIAGNOSTIC
LOOPBACK
RCLKO
Table 9-5 identifies the source of the output signal RCLKO based on certain variables and register bits.
Table 9-5. Source Selection of RCLKO Clock Signal (Internal Rx Clock)
SIGNAL
LOOPT
PORT.CR3
LBM[2:0]
( PORT.CR4 )
LIUEN
CLADC
( PORT.CR3 )
SOURCE
1 XXX 1 X Rx LIU
1 XXX 0 X RLCLK
0 DLB disabled 1 X Rx LIU
0
DLB disabled & ALB
disabled
0 X RLCLK
0 DLB (1XX) X 0 CLAD
0 DLB (1XX) or ALB (001) 0 1 TCLKI
RCLKO
0 DLB (1XX) 1 1 TCLKI
9.2.3 Line IO Pin Timing Source Selection
The line IO pins can use any input clock pin (RLCLK or TCLKI) or output clock pin (TLCLK, RCLKO, or TCLKO) for
its clock pin and meet the AC timing specifications as long as the clock signal is valid for the mode the part is in.
The clock select bit for the transmit line IO signal group
PORT.CR3 .TLTS selects the correct input or output clock
timing.