Hdlc.tsrl, Hdlc.tsrie – Rainbow Electronics DS3170 User Manual
Page 158
DS3170 DS3/E3 Single-Chip Transceiver
158 of 233
Register Name:
HDLC.TSRL
Register Description:
HDLC Transmit Status Register Latched
Register Address:
0A6h
Bit
# 15 14 13 12 11 10 9 8
Name
-- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name -- -- TFOL TFUL TPEL -- TFEL THDAL
Bit 5: Transmit FIFO Overflow Latched (TFOL) – This bit is set when a Transmit FIFO overflow condition occurs.
Bit 4: Transmit FIFO Underflow Latched (TFUL) – This bit is set when a Transmit FIFO underflow condition
occurs. An underflow condition results in a loss of data.
Bit 3: Transmit Packet End Latched (TPEL) – This bit is set when an end of packet is read from the Transmit
FIFO.
Bit 1: Transmit FIFO Empty Latched (TFEL) – This bit is set when the TFE bit transitions from 0 to 1.
Note: This bit is also set when HDLC.TCR.TFRST is deasserted.
Bit 0: Transmit HDLC Data Available Latched (THDAL) – This bit is set when the THDA bit transitions from 0 to
1.
Note: This bit is also set when HDLC.TCR.TFRST is deasserted.
Register Name:
HDLC.TSRIE
Register Description:
HDLC Transmit Status Register Interrupt Enable
Register Address:
0A8h
Bit
# 15 14 13 12 11 10 9 8
Name
-- -- -- -- -- -- -- --
Default
0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name -- --
TFOIE
TFUIE
TPEIE -- TFEIE
THDAIE
Default
0 0 0 0 0 0 0 0
Bit 5: Transmit FIFO Overflow Interrupt Enable (TFOIE) – This bit enables an interrupt if the TFOL bit is set and
the bit in
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 4: Transmit FIFO Underflow Interrupt Enable (TFUIE) – This bit enables an interrupt if the TFUL bit is set
and the bit in
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Transmit Packet End Interrupt Enable (TPEIE) – This bit enables an interrupt if the TPEL bit is set and the
bit in
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled