Rainbow Electronics DS3170 - Manual (Page 67)

DS3170 DS3/E3 Single-Chip Transceiver
67 of 233
Table 9-12. Global 8 kHz Reference Source Table
GL.CR2.
G8KIS
GL.CR2.
G8KRS[1:0]
SOURCE
0 00 None, the 8KHZ divider is disabled.
0 01 Derived from CLAD output clock
0 10 8KREF source selected by P8KRS[1:0]
0 11 Undefined
1 XX GPIO4
Table 9-13 lists the selectable sources for port 8 kHz reference sources.
Table 9-13. Port 8 kHz Reference Source Table
PORT.CR3 .P8KRS[1:0] SOURCE
0X Undefined
10 Internal receive framer clock
11 Internal transmit framer clock
Figure 9-6 shows the 8 kHz reference logic tree.
Figure 9-6. 8KREF Logic
CLOCK DIVIDER
CLOCK DIVIDER
TX CLOCK
RX CLOCK
FRAME MODE
P8KRS
GPIO4
DS3 CLK
E3 CLK
FROM CLAD
FRAME MODE
G8KRS
G8KIS
GLOBAL 8KREF
PORT 8KREF
9.4.3 One Second Reference Generation
The one second reference signal is used as an option to update the performance registers on a precise one
second interval. The generated internal signal should be about 50% duty cycle and it is derived from the Global 8
kHz reference signal by dividing it by 8000. The low to high edge on this signal will set the
GL.SRL. ONESL latched
one second detect bit which can generate an interrupt when the GL.SRIE. ONESIE interrupt enable bit is set. The
low to high edge can also be used to generate performance monitor updates when GL.CR1. GPM[1:0]=1X.