Rainbow Electronics DS3170 - Manual (Page 4)

DS3170 DS3/E3 Single-Chip Transceiver
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TABLE OF CONTENTS
1 BLOCK DIAGRAMS 2
2 APPLICATIONS 12
3 FEATURE DETAILS 13
3.1 G LOBAL F EATURES ........................................................................................................................................ 13
3.2 R ECEIVE DS3/E3 LIU F EATURES .................................................................................................................. 13
3.3 J ITTER A TTENUATOR F EATURES ..................................................................................................................... 13
3.4 R ECEIVE DS3/E3 F RAMER F EATURES ........................................................................................................... 13
3.5 T RANSMIT DS3/E3 F ORMATTER F EATURES .................................................................................................... 14
3.6 T RANSMIT DS3/E3 LIU F EATURES ................................................................................................................. 14
3.7 C LOCK R ATE A DAPTER F EATURES ................................................................................................................. 14
3.8 HDLC C ONTROLLER F EATURES ..................................................................................................................... 14
3.9 FEAC C ONTROLLER F EATURES ..................................................................................................................... 14
3.10 T RAIL T RACE B UFFER F EATURES ................................................................................................................... 15
3.11 B IT E RROR -R ATE T ESTER (BERT) F EATURES ................................................................................................ 15
3.12 L OOPBACK F EATURES ................................................................................................................................... 15
3.13 M ICROPROCESSOR I NTERFACE F EATURES ..................................................................................................... 15
3.14 S LAVE S ERIAL P ERIPHERAL I NTERFACE (SPI) F EATURES ................................................................................ 15
3.15 T EST F EATURES ............................................................................................................................................ 15
4 STANDARDS COMPLIANCE 16
5 ACRONYMS AND GLOSSARY 17
6 MAJOR OPERATIONAL MODES 18
6.1 DS3/E3 F RAMED LIU M ODE .......................................................................................................................... 18
6.2 DS3/E3 U NFRAMED LIU M ODE ..................................................................................................................... 20
6.3 DS3/E3 F RAMED POS/NEG M ODE ............................................................................................................... 21
6.4 DS3/E3 U NFRAMED POS/NEG M ODE .......................................................................................................... 22
6.5 DS3/E3 F RAMED UNI M ODE ......................................................................................................................... 23
6.6 DS3/E3 U NFRAMED UNI M ODE ..................................................................................................................... 24
7 PIN DESCRIPTIONS 25
7.1 S HORT P IN D ESCRIPTIONS ............................................................................................................................. 25
7.2 D ETAILED P IN D ESCRIPTIONS ......................................................................................................................... 27
7.3 P IN F UNCTIONAL T IMING ................................................................................................................................ 37
7.3.1 Line IO.................................................................................................................................................. 37
7.3.2 DS3/E3 Framing Overhead Functional Timing .................................................................................... 40
7.3.3 DS3/E3 Serial Data Interface............................................................................................................... 41
7.3.4 Microprocessor Interface Functional Timing ........................................................................................ 43
7.3.5 JTAG Functional Timing....................................................................................................................... 50
8 INITIALIZATION AND CONFIGURATION 51
8.1 M ONITORING AND D EBUGGING ....................................................................................................................... 52
9 FUNCTIONAL DESCRIPTION 53
9.1 P ROCESSOR B US I NTERFACE ......................................................................................................................... 53
9.1.1 SPI Serial Port Mode............................................................................................................................ 53
9.1.2 8/16 Bit Bus Widths.............................................................................................................................. 53
9.1.3 Ready Signal ( RDY ) ............................................................................................................................. 53
9.1.4 Byte Swap Modes ................................................................................................................................ 53
9.1.5 Read-Write/Data Strobe Modes........................................................................................................... 53
9.1.6 Clear on Read/Clear on Write Modes .................................................................................................. 53
9.1.7 Interrupt and Pin Modes....................................................................................................................... 54
9.1.8 Interrupt Structure ................................................................................................................................ 54
9.2 C LOCKS ........................................................................................................................................................ 55
9.2.1 Line Clock Modes................................................................................................................................. 55
9.2.2 Sources of Clock Output Pin Signals ................................................................................................... 57
9.2.3 Line IO Pin Timing Source Selection ................................................................................................... 59
9.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 62