Rainbow Electronics DS3170 - Manual (Page 15)

DS3170 DS3/E3 Single-Chip Transceiver
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3.10 Trail Trace Buffer Features
§ Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register
§ Insertion of the outgoing trail access point identifier from a 16-byte transmit register
§ Receive trace identifier unstable status indication
3.11 Bit Error-Rate Tester (BERT) Features
§ Generates and detects pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
§ Supports pattern insertion/extraction in DS3/E3 payload, or entire data stream
§ Large 24-bit error counter allows testing to proceed for long periods without host intervention
§ Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
§ Off-line monitoring on the Receive BERT
3.12 Loopback Features
§ LIU terminal loopback (transmit to receive) - ALB
§ Line facility loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - LLB
§ Framer diagnostic loopback (transmit to receive) with optionally transmitting unframed all-one signal toward
line/tributary interface - DLB
§ Simultaneous line facility loopback (LLB) and framer diagnostic loopback (DLB)
§ Framer payload loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - PLB
3.13 Microprocessor Interface Features
§ Multiplexed or nonmultiplexed 8- or 16-bit control port
§ Intel and Motorola bus compatible
§ Global reset input pin
§ Global interrupt output pin
§ Eight programmable I/O pins (GPIOx)
3.14 Slave Serial Peripheral Interface (SPI) Features
§ Three-wire synchronous serial data link operating in full duplex slave mode up to 10 Mbps
§ Glueless connection and fully compliant to Motorola popular communication processors such as MPC8260 and
microcontrollers such as M68HC11
§ Software provision ability for active phase of the serial clock (i.e. rising edge versus falling edge), bit ordering of
the serial data (most significant first versus least significant bit first)
3.15 Test Features
§ Five pin JTAG port
§ All functional pins are inout pins in JTAG mode
§ Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
§ Custom JTAG instructions to use RAM BIST
§ RAM BIST on all internal RAM
§ HIZ pin to force all digital output and inout pins into HIZ
§ TEST pin for manufacturing scan test modes